ROM addresses are read the other way around

[Sally000]

I have a parallel to serial converter which connects to three series shift registers. this connects to a ROM. the ROM addresses are read by taking bits from the parallelto serial converter output,and from the outputs from each shift register.
my problem is I am reading the addresses the other way around.

the vhdl code for the parallel to serial converter and shift registers are shown below,


library ieee;
use ieee.std_logic_1164.all;

entity parallel_to is
port(
d:in std_logic_vector (3 downto 0);
Clk,load: in std_logic;
D_out : out std_logic
);
end parallel_to;

architecture serial of parallel_to is
signal reg: std_logic_vector(3 downto 0);
begin
Process (Clk)
Begin
If (clk'event and Clk='1') then
if (load='1') then reg <= d;
else reg <= reg (2 downto 0) & '0';
end if;
end if;
end process;
D_out <= reg(3);
end serial;




library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
port(Clk, SI, S : in std_logic;
SO : out std_logic);
end shift_register;
architecture Shift_archi of shift_register is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clk, S)
begin
if (Clk'event and Clk='1') then
if (S='1') then
tmp <= (others => '1');
else
tmp <= SI &tmp(3downto 1);
end if;
end if;
end process;
SO <= tmp(0);
end Shift_archi;


what should I change to get the ROM addresses the other way around

 

[jeandelfrigo]

Hello Sally000,

I do not fully understand the entire system from your explanation, I'm sorry.

But what I do notice is that your parallel to serial converters shifts left or MSB (=3) first , but the shift register shifts right LSB (=0) first.

I would try making both the same shift direction. Because I do not have more information on the entire system I cannot say which one needs to change.

Regards,

jeandelfrigo

 

[Sally000]

Thanks for the reply jeandelfrigo..
yes that was the problem