QSIG Release 7.5

[357951258]

The CS1000e is running include latest pages and loadware however there is still a problem .
I setup QSIG Trunck on MGC 4 0 ( ISIG Protokoll) on slot 4 0 1.
When i start fdl Msdl appears first this message :


INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE


INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE
INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE
INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE
OK

For a short time d chanel change to establish
then appears many dta300 until message DCH055 DCH: 53 RLS NO RESPONSE TIME: 18:32:08 14/11/2012

Any ideas ?

 

[KCFLHRC]

Disable the TMDI card and then force download it. It should enable on it's own after the FDL. Then disable it. Then enable it without the force download. Then enable the loop and see if the d-channel establishes. Those TMDI cards are weird. This is a solution I have used and works for me.

 

[357951258]

Thanks ,but doesnt help

 

[KCFLHRC]

Put a loop back plug on it and see if the d-channel comes up in wrong mode

 

[KCFLHRC]

You can also try doing a self test on the card

 

[KCFLHRC]

Command in LD 96 would be SLFT TMDI 4 0 1

 

[357951258]

Thanks self test is still passed successful
Loop is going wrong mode and so 2 up to minutes later the d channel reports no response

 

[KCFLHRC]

Is the far end connected so the d-channel will establish?

 

[357951258]

After remove PRI Card and set back .
FDL msdl and dch include the messages

INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE
INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE
INFO1807 PLEASE WAIT UP TO 40 SECONDS FOR CARD RESPONSE

The d channel reports establish first
Then starts the DTA300 SLP
a little later d channel send rls no response .

The same soloution in MGC 0 0 runs well

 

[KCFLHRC]

Do you have DSP resources defined and are they idle in Loop 4 0 ?

 

[357951258]

DSP's are o.k.

 

[KCFLHRC]

So it works fine in MGC 0 0. Do you have a clock source defined in 4 0 and a clock controller on board ? In a 1000 E you have to have a clock reference defined in each loop because the clock signals aren't passed over ethernet.

 

[357951258]

The clock source tracks over ELAN .( NTP Planing engineering CS1000 E
We have systems allready running.
But thanks anyway

 

[KCFLHRC]

You would be wrong about that, But good luck with it. Directly from the NTP

ATTENTION
IMPORTANT!
Every Small System cabinet or Media Gateway that contains a digital trunk must
contain a clock controller.

 

[357951258]

I've you are right i'm sorry
Tomorrow i get information from avaya support