Problem with simalution : TImer code

[clementval]

Hi !

I have a problem when I'm simulating this code !

The process run right but when I'll copy the vector on the output my value are changing with X state but it should be 1

use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;


entity time_set is
port(selected, run, minup, mindown, hrup, hrdown, reset : IN std_logic;
min0, min1, min2, min3, min4, min5 : OUT std_logic);
end entity time_set;

architecture a_time_set of time_set is

signal minute : std_logic_vector(5 downto 0) := "000000";




begin
min0 <= minute(0);
min1 <= minute(1);
min2 <= minute(2);
min3 <= minute(3);
min4 <= minute(4);
min5 <= minute(5);

min_set_pr rocess(minup, mindown, reset)
begin
if(rising_edge(reset)) then
minute <= "000000";
else
if(rising_edge(minup)) then
if(selected = '1') then
if(run = '0') then
if(minute = "111011") then
minute <= "000000";
else
minute <= std_logic_vector(unsigned(minute) +1);
end if;
end if;
end if;
elsif(rising_edge(mindown)) then
if(selected = '1') then
if(run = '0') then
if(minute = "000000") then
minute <= "111011";
else
minute <= std_logic_vector(unsigned(minute) -1);
end if;
end if;
end if;
end if;
end if;
end process min_set_pr;
end architecture a_time_set;

 

[blacktom]

Hello Clementval,

X's means usually unknown value's.
Are you sure you have a proper reset during simulation?

Good luck