Problem adding two integers

[cdchilds]

Hi,

I am trying to add an integer to an integer variable in VHDL, but when I try to synthesise it in XST I get:

"ERROR:Xst:1549 - controller.vhd line 331: Range bound must be a constant."

I have a bus (7 downto 0) that I convert to an integer using CONV_INTEGER, then try to add it to a variable using the following code:

totalLogCount := totalLogCount + CONV_INTEGER(internalBus);

The definitions are:

variable totalLogCount : integer;
and
internalBus : inout std_logic_vector(7 downto 0);

I use similar lines elsewhere in the code, but only ever adding 1 (e.g. "x := x + 1;&quot, and this seems to be synthesisable.

Any help would be most appreciated.

Thanks,

Chris.

 

[cdchilds]

Sorry, that is the wrong error message. The correct one is:

"ERROR:Xst:677 - controller.vhd line 330: Illegal constants on arithmetic operators."

Apologies for being dumb

Chris.

 

[senjed]

I don't know exactly what this error means, but I think you should first convert the std_logic_vector to unsigned or signed, and then to integer. this needs the std_logic_unsigned and std_logic_signed libraries to be defines (with USE). I have always done it that way, and never have encountered such errors

 

[cdchilds]

Thanks senjed, I think I have heard something like that before. For the time being I have recoded my design to avoid the issue, but I'm sure it will appear again before too long

Chris.