I need help to program a polyphase filter in VHDL, there are 3 component to program which is delay(flip flop), multiplier and add up function. And i think flip flop is not a problem for me, but i have no idea how to program the multiplier part and add up part...Anyone can help?
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polyphase filter in vhdl
- Thread starter 020483
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I presume you need the floating point multiplier, available for synthesis. (For fixed point or for the REAL type you just write a*b, providing the appropriate library & package).
Traditionally the floating point artihmetics modules were offered as IP soft cores for rather big cash.
Since last year however there is a library by IEEE available for free with several floating point arithmetic functions implemented for std_logic_vector represented data. You shall just find it and accept the data format used there ...
Just in case: if you didn't like that one and your target was commercial we could discuss some other solution ...
rgds
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