pls help, no programing option

[naqiboy]

Hi guys
i wrote this code for a simple counter , 1 to 9. Apparently, it compiles properly including pin assignments but when i go to program, nothing show up on there. Ive tried other vhdl projects and they program fine. any ideas?

thanks!

code---------
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY counter IS

PORT (CLOCK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
End counter;



ARCHITECTURE mylogic OF counter IS

signal count : std_logic_vector (25 DOWNTO 0);
signal a : std_logic;
signal D : std_logic_vector (3 DOWNTO 0);

BEGIN PROCESS (CLOCK)
BEGIN

IF (CLOCK'EVENT AND CLOCK = '1') THEN

count <= count + 1;

END IF;

IF count = "01011111010111100001000000" THEN
a<='0';
END IF;

IF count = "101111101011110000100000000" THEN
a<='1';

count<="00000000000000000000000000";

END IF;



IF (a'EVENT AND a = '1') THEN

D <= D + 1;


IF D = "1001" THEN

D<="0000";

END IF;

END IF;



S(0) <= not ((not D(2) and not D(0)) or (D(2) and D(0)) or D(3) or D(1));
S(1) <= not ((not D(0) and not D(1)) or (D(1) and D(0)) or (not D(2)));
S(2) <= not ((not D(1)) or D(0) or D(2)) ;
S(3) <= not ((not D(2) and not D(0)) or (D(2) and D(0) and not D(1)) or (not D(2) and D(1)) or (D(1) and not D(0)));
S(4) <= not ((not D(2) and not D(0)) or (not D(0) and D(1)));
S(5) <= not ((not D(1) and not D(0)) or (D(2) and not D(0)) or D(3) or (not D(1) and D(2)));
S(6) <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));



END PROCESS;
END mylogic;

 

[jeandelfrigo]

Nagiboy,

Stick to the rules my friend.

In synchronous design only one signal in the sensitivity list being the clock (except for an asynchronous set or reset if you really want/need this).

Also take my advise and stick to using one clock per process it keeps the code more understandable and you depend less on the intelligence of the implementation tool.

What I think is the problem with your code is the following:

the process gets triggered only by the clock signal (this is good). So the first part is OK, but then you mess up.

You check for the rising edge of a but there is no a in the process sensitivity list. Also Is a intended to be a clock if not do not use that statement but use a and a one clock delayed a to detect the rising edge.

What happend I think is the following.

The simulator made the best of the code as it is written, but once you implement the code then I think the problem is that the tool does not recognize a flip flop for D. depending on the tool it will generate error or warning or do the best it can.

What the hell is all the S stuff doing at that position in the process. A simulator might perform the statements whenever clock chenges but a synthesis tool will be lost.


Another tip, use tabs or space to make the code more readable.

So i've re-written your code with the following assumptions:

a is a divided version of the master clock clock and you wnat the S outputs registered on clock a (good thing to do when you go to the outside world)


Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


ENTITY counter IS

PORT (
CLOCK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
end counter;

ARCHITECTURE mylogic OF counter IS

signal count : std_logic_vector (25 DOWNTO 0);
signal a : std_logic;
signal D : std_logic_vector (3 DOWNTO 0);


BEGIN
-- dividing the base clock
PROCESS (CLOCK)
BEGIN
IF (CLOCK'EVENT AND CLOCK = '1') THEN
IF count = "01011111010111100001000000" THEN
a<='0';
elsif count = "101111101011110000100000000" THEN
a<='1';
count<="00000000000000000000000000";
else
count <= count + 1;
END IF;
end if;
end process;

-- process on divided clock
process(a)
begin
IF (a'EVENT AND a = '1') THEN
IF D = "1001" THEN
D<="0000";
else
D <= D + 1;
end if;
S(0) <= not ((not D(2) and not D(0)) or (D(2) and D(0)) or D(3) or D(1));
S(1) <= not ((not D(0) and not D(1)) or (D(1) and D(0)) or (not D(2)));
S(2) <= not ((not D(1)) or D(0) or D(2)) ;
S(3) <= not ((not D(2) and not D(0)) or (D(2) and D(0) and not D(1)) or (not D(2) and D(1)) or (D(1) and not D(0)));
S(4) <= not ((not D(2) and not D(0)) or (not D(0) and D(1)));
S(5) <= not ((not D(1) and not D(0)) or (D(2) and not D(0)) or D(3) or (not D(1) and D(2)));
S(6) <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));
end if;
end process;
END mylogic;

I've added priority encoding in the IFs this makes the code more readable and reliable.

When writing basic stuff like this try imagining what hardware this would give, if you're new then it's best to draw it out. Even experienced VHDL programmers make different level blockdiagrams and sometimes timing diagrams of their code, and most of them (including myself) started out doing that for basic designs.

good luck

jeandelfrigo