Phase Shifting 1

[Nilak]

Just wondering if there's a more efficient way of creating two phase shifted signals which are going to be used later for sampling. Also, is it possible to create a phase shifted signal running at the maximum frequency of the clock? my guess is no, but maybe i'm wrong.

here's what i came up with.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity phase_shift is
Port ( clock : in std_logic;
clock_out : out std_logic; --NOTE: phase shifted and non-phase shifted clocks
clock_out90 : out std_logic); --are half the frequency of the clock.
end phase_shift;

architecture Behavioral of phase_shift is
signal sig1 : std_logic := '0';
signal sig2 : std_logic := '0';
begin
no_phase_shiftrocess(clock)
begin
-- sig1 <= clock; doesn't work
if clock'event and clock = '0' then
sig1 <= not sig1;
else
sig1 <= sig1;
end if;
end process;
clock_out <= sig1;

phase_shiftrocess(clock)
begin
-- sig2 <= clock; doesn't work
if clock'event and clock='1' then
sig2 <= not sig2;
else
sig2 <= sig2;
end if;
end process;
clock_out90 <= sig2;

end Behavioral;

 

[VHDLguy]

For a while I thought you had screwed up here, but now I see that you mention the resulting clocks are half the frequency. I couldn't figure out how you thought you had a 90 phase shift between the two signals. But you are actually saying that the clock_out90 edge is 90 from the original clock edge.

to do this without a frequency change you either need a different clock that is faster, or by making use of a PLL built into your FPGA, or a standard block provided by your fab house if you are working on an ASIC.

Your else conditions are not really valid vhdl (because its outside the 'event area), but since you only assigned the signal to itself the synthesizer would ignore it.


--

http://www.lateralsands.com/

 

[Nilak]

Thanks for the input.

 

[Nilak]

Oh yeah, i don't understand why the else conditions are not valid. Also, the clock_out90 is actually phase shifted with respect to the clock_out signal, not the input clock signal (where both of these signals are half the frequency of the original clock). at least that's what the test bench showed. another question, do you think i would be able to use these two signals (clock_out and clock_out90) as clocks for other signals (since i haven't tried using them for anything yet).

 

[VHDLguy]

sorry, yes I got myself confused there with regard to what was shifted in relation to what.

as far as using these clocks go - no problem - you may need to assign them as clocks, (and indicate their speed) depending on what software you are using. But they should be fine to use.

As far as the else condition goes, you are mixing clocked logic and combinatorial logic, in this case you are simply stating the sig2 (or 1) remains the same, so its not really needed, but if you were to say sig2 <= some_other_signal; then you have a mixture of a combinatorial circuit with a clocked circuit. Now I would assume that you are trying to create a Mux after your flip-flop and you want to use the Flip-flop output when clock = '1' and some_other_signal when clock = '0'. but the synthesizer doesn't figure that out.

I actually tried your code, but with a random register as the else condition and i got a combinatorial loop warning. The resulting circuit was simply an inverter. No sign of a flip-flop anywhere, nothing even close to what you wanted.

the second else would have to go in a seperate process to get the desired mux.

Of course in your situation leaving the else off is the same circuit since you simply assigned the signal to itself.

--

http://www.lateralsands.com/

 

[VHDLguy]

let me clarify, why can't the synthesizer handle the example?

because you are asking it to do it with one driver. knowing what you really meant is simple to me as I am not limiting myself to creating the circuit with one driver. but inorder to get that result from the synthesizer you need to have different signal names. I guess my telling you to do it in a different process is not really the answer, different signal names are the answer. but you shouldn't mix clocked signals and combinatorial signals in the same process, so it still stands that you need a new process.

--

http://www.lateralsands.com/