PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GHz, the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express currently runs at 2.5Gbps, or 250MBps per lane in each direction, providing a total bandwidth of 16GBps in a 32-lane configuration. Future frequency increases will scale up total bandwidth to the limits of copper and significantly beyond that via other media without impacting any layers above the Physical Layer in the protocol stack. PCI Express provides I/O attach points for high-performance graphics, 1394b, USB 2.0, InfiniBand™ Architecture, Gigabit networking and so on.
------------------
For specification links and such, please refer to the original articlel found here:
------------------
For specification links and such, please refer to the original articlel found here:
