Partial Multiplier

[VHDLVLSI]

Hi,
Can some one help me out with the following?

I am designing a Muliplier in VHDL such that A, B are multiplicand and multiplier respectively, where they are 3-bits wide each.
Outputs are two partial products PP1 and PP2 [ of width >=(3+3+2) = 9 bits each ], where the sum of PP1 and PP2 is the actual product of A and B.

The partial products output should be as follows.(For convenience, all values are in decimals, while the actual outputs should be 9-bits wide std_logic_vectors)

A B PP1 PP2
-----------------------
1 7 5 2
2 7 14 0
3 7 11 10
4 7 8 20
5 7 13 22
6 7 22 20
7 7 19 30

7 1 3 4
7 2 12 2
7 3 15 6
7 4 12 16
7 5 15 20
7 6 16 26
7 7 19 30

6 1 2 4
6 2 12 0
6 3 14 4
6 4 8 16
6 5 10 20
6 6 20 16
6 7 22 20

5 1 1 4
5 2 8 2
5 3 9 6
5 4 4 16
5 5 5 20
5 6 12 18
5 7 13 22

4 1 0 4
4 2 8 0
4 3 8 4
4 4 0 0
4 5 0 0
4 6 8 8
4 7 8 8

1 4 4 0
2 4 8 0
3 4 12 0
4 4 0 16
5 4 4 16
6 4 8 16
7 4 12 16

Thanks.
VHDLVLSI

 

[12341234]

Hi,
I hope anyone can help me.
I want to have vhdl modling of a low power multiplier with fixed-point multiplying that will be synthesiable.
the a,b are inputs(16 bit) and the output will be the same bits.(16 bit).