Parallel to Serial Conversion

[Nilak]

I'm attempting a parallel to serial conversion but i'm having difficulties implementing it. i have two signals (ImodDATA and QmodDATA) 11-bits wide that are concatinated with 3 more bits to yield the desired 14-bit dataOUT output. there are some conditions as described in the code, but the problem is that I want QmodDATA to follow ImodDATA hence the parallel to serial conversion. Now, I assume this can be done with shift registers and maybe using an inout temp signal but I am uncertain as how to proceed. Any help would be greatly appreciated.

btw, sampleCLKreqINDV is a sampling clock of the ImodDATA and QmodDATA. Should I instead use a sample clock twice the frequency and just trigger at the rising edge when implementing the shift register or can i still trigger at the falling edge. The problem here is that dataOUT is multisourced

OVERSAMPLE_DATA1: process(sampleCLKreqIN0, ImodDATA, QmodDATA)
begin
if rising_edge(sampleCLKreqINDV) then --100MHz Clock.
if (ImodDATA(10) = '1') then
dataOUT <= "111" & ImodDATA;
elsif (ImodDATA(10) = '0') then
dataOUT <= "000" & ImodDATA;
end if;
else if
end if;
end process;

OVERSAMPLE_DATA2: process(sampleCLKreqINDV, ImodDATA, QmodDATA)
begin
if falling_edge(sampleCLKreqINDV) then
if (QmodDATA(10) = '1') then
dataOUT <= "111" & QmodDATA;
elsif (QmodDATA(10) = '0') then
dataOUT <= "000" & QmodDATA;
end if;
end if;
end process;

 

[Nilak]

I tinkered with the code a bit more and got the result below which I think is more reasonable, but still not sure if it's the right approach.

SER_TO_PAR_AND_OVERSAMP: process(sampleCLKreqIN0, ImodDATA, QmodDATA)
begin
if (reset = '1') then
dataOUT <= (others => '0');
dataIQselect <= IchanSELECT;
elsif rising_edge(sampleCLKreqIN0) then --100MHz Clock.
if (dataIQselect = IchanSELECT) then
if (ImodDATA(10) = '1') then
dataOUT <= "111" & ImodDATA;
elsif (ImodDATA(10) = '0') then
dataOUT <= "000" & ImodDATA;
end if;
dataIQselect <= QchanSELECT;
elsif (dataIQselect = QchanSELECT) then
if (QmodDATA(10) = '1') then
dataOUT <= "111" & QmodDATA;
elsif (QmodDATA(10) = '0') then
dataOUT <= "000" & QmodDATA;
end if;
dataIQselect <= IchanSELECT;
end if;
end if;
end process;

 

[Nilak]

Forgot to add that the clock (sampleCLKreqIN0 @ 100MHz) is now TWICE the frequency of ImodDATA and QmodDATA (@50MHz).