Hey everyone. This is my first time dealing with VHDL, and I'm kinda lost. I'm hoping that you guys can give me some pointers.
1) I see that there are two types. There's the "Entity **" and the "Architecture Behv". When programming, do I have to include both? Or is one enough?
2) If i were to make a Gate network that did the following:
x0, x1', x2' goes into m1 which is an and gate (m1)
x0', x1, x2' goes into m2 which is an and gate (m2)
x0', x1, x2 goes into m6 which is and and gate (m6)
and then m1, m2, m6 goes into an or gate, which spits out Z.
How would I proceed? thanks
1) I see that there are two types. There's the "Entity **" and the "Architecture Behv". When programming, do I have to include both? Or is one enough?
2) If i were to make a Gate network that did the following:
x0, x1', x2' goes into m1 which is an and gate (m1)
x0', x1, x2' goes into m2 which is an and gate (m2)
x0', x1, x2 goes into m6 which is and and gate (m6)
and then m1, m2, m6 goes into an or gate, which spits out Z.
How would I proceed? thanks