New to VHDL

[OOP]

Hi all,

I'm currently doing a project concerning VHDL. I would like to ask if anyone can direct me to places where there are some sample VHDL projects for me to work on and practise.

Any help / advise will be appreciated.
Thanks.

By the way, i'm using Xilinx ISE 7.1 and i'm not sure why I cannot simulate my simple comparator? Anyone also uses Xilinx ISE webpack here?

Thanks for reading

 

[mptech]

Hi,
There are already many inbuilt examples in XILINX webpack. You can used Modelsim Xilinx Starter (Free edition from XILINX) to simulate those projects and get some feelings.

if you have any further question just ask
mptech