need help with synchronous input vs. clock

[steadyeddie]

Hi folks. I've been struggling with a problem with synchronous circuits in VHDL. Let's say that I have a clock feeding into two logic blocks that operate in parallel. The two blocks are mealey state machines.

The first block generates output that is used as input for the second block.

There are no modeled delays, therefore, this should work properly.

The problem I have is this: When the inputs change in value, they do so at the exact same time as the next rising clock edge. On the next rising clock edge, the second block needs to read that input, but since the signal changes value at the exact same time as the clock rises, the second block doesn't register the change in value!!

The solution I can think of is this:

1) Either delay the clock that goes into the second state machine.

2) Or change the output of the signal on the first state machine faster.

So which one do I choose, and I how do I do this? The real problem I have with the first method is that I can't use wait blocks in process statements with sensitivity lists.

please help. I know the solution must be simple, but it's puzzling me to no end.

 

[Srika]

The first solution u've supplied is not a proper solution because if u delay the clock pulse then the parallelism is lost.I'd suggest to make the second process sensitive to the first output signal,and check for the clock'event and clk=1 in the same.This is the general solution of the problem u faced.

 

[steadyeddie]

srika,

Thanks for the reply. I'll try your solution and see what happens.

 

[dd202]

Hi,

please can anyone tell me if the code i have written below is correct and working. it has two state machines. one reads the register and the other writes to the register. should i use signal PIW_Internal or declare a global variable. i understand that the code has little meaning if not combined with all the codes. but any kind of comments or correction necessary will be much appreciated.
thanks
dipayan


library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity PIW_Register is
port ( Write_Reg, clock, reset, PIW_Fetch : in std_logic;
PIW_Acq : in std_logic_vector (23 downto 0);
PIW_Out : out std_logic_vector (23 downto 0);
Reg_Write_Complete : out std_logic;
Reg_Ready : out std_logic);
end entity PIW_Register;

architecture RTL of PIW_Register is
type state_read is (start_read, Read_Register);
type state_write is (start_write, Write_Register);
signal present_state_read, next_state_read : state_read;
signal present_state_write, next_state_write : state_write;
signal PIW_Internal : std_logic_vector (23 downto 0) := x"000000";

begin
seq : process (clock, reset)
begin
if (reset = '1') then
present_state_read <= start_read;
present_state_write <= start_write;
else if rising_edge(clock) then
present_state_read <= next_state_read;
present_state_write <= next_state_write;
end if;
end if;
end process seq;

com_read : process (present_state_read, PIW_Fetch)
begin
Reg_Ready <= '0';
case present_state_read is

when start_read =>
Reg_Ready <= '0';
if (PIW_Fetch = '1') then
next_state_read <= Read_Register;
else next_state_read <= start_read;
end if;

when Read_Register =>
PIW_Out <= PIW_Internal;
Reg_Ready <= '1';
if (PIW_Fetch = '0') then
next_state_read <= start_read;
else next_state_read <= Read_Register;
end if;

end case;
end process com_read;

com_write : process (present_state_write, Write_Reg)
begin
Reg_Write_Complete <= '0';

case present_state_write is

when start_write =>
Reg_Write_Complete <= '0';
if (Write_Reg = '1') then
next_state_write <= Write_Register;
else next_state_write <= start_write;
end if;

when Write_Register =>
PIW_Internal <= PIW_Acq;
Reg_Write_Complete <= '1';
if (Write_Reg = '0') then
next_state_write <= start_write;
else next_state_write <= Write_Register;
end if;

end case;
end process com_write;
end architecture RTL;