N times concatenation

[RVSachin]

I would like to know as to how can I achieve the following in VHDL.

Assume widths of data_in = n and data_out = k*n, where k is a positive integer >2.
I want to concate data_in k times and finally assign it to data_out.

i.e.,
if k = 4 and n = 3 with value of data_in = "100" then
data_out = "100" & "100" & "100" & "100" ;
= "100100100100";

Please help.

[ RVSachin ]

 

[ahedin]

library ieee;
use ieee.std_logic_1164.all;

entity temp4 is

generic(K : positive := 4;
N : positive := 3);

port (Din : in std_logic_vector(N-1 downto 0);
Dout : out std_logic_vector((N*K)-1 downto 0));

end temp4;

architecture test of temp4 is

begin

main : process(Din)
begin

for i in 0 to K-1 loop

Dout(N+N*I-1 downto N*I) <= Din;

end loop;

end process;

end test;