Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

Register Log in
  • Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Logic space

Status
Not open for further replies.
noOne2556

noOne2556

Technical User
Jan 25, 2002
5
GB
I have to justify why I have used certain methods and not others for a project, I have tried IF, WHEN, and a state_vec model, I used the state_vec model, cause it worked but how much logic do IF and WHEN statements use compared to the others?

AnDy
 
Sort by date Sort by votes
If at all u could be a bit more clear,I appreciate that?

sri
 
Upvote 0 Downvote
If at all u could be a bit more clear,I'd appreciate that?

sri
 
Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Olivier2412
  • Locked
  • Question
Generate a 2 µs high level logic with a 10 MHz clock ?
Replies
0
Views
38
Olivier2412
Olivier2412
meganwhite
  • Locked
  • Question
minimize logic
Replies
1
Views
28
VHDLguy
VHDLguy
Vazquez78
  • Locked
  • Question
How can I program a logic device with the tool ispLEVER from Lattice?
Replies
0
Views
47
Vazquez78
Vazquez78
byoung
  • Locked
  • Question
VHDL logic error
Replies
2
Views
39
sunil287
sunil287

Part and Inventory Search

Sponsor

Back
Top