integers on 32 bit counter 1

[philrivers]

Hi, I imagine this is going to seem like a rookie mistake. i am doing some work on developing an algorithm the cod eof which i will post below. essentially it isnt finished so, but before i go further i would like to rectify the mistakes that are appearing with regards to the constants. "Numeric value exceeds INTEGER high" is appearing. how can I fix this
thanks

LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;



ENTITY cordic IS

PORT (
clk : IN STD_LOGIC;
load: IN STD_LOGIC;
res : IN STD_LOGIC;

x_in, IN STD_LOGIC_VECTOR(15 downto 0);
y_in, IN STD_LOGIC_VECTOR(15 downto 0);
z_in: IN STD_LOGIC_VECTOR(15 downto 0);

x_out: OUT STD_LOGIC_VECTOR(15 downto 0);
y_out: OUT STD_LOGIC_VECTOR(15 downto 0);

END cordic;

ARCHITECTURE cordic_arch OF cordic IS

constant K : signed(31 down to 0) := SIGNED(To_StdLogicVector(100100001100100000101001100011)); -- .607252935
constant a : signed(31 down to 0) := SIGNED(To_StdLogicVector(111011100110101100101000000000)); -- 1.0
constant b : signed(31 down to 0) := SIGNED(To_StdLogicVector(11101110011010110010100000000)); -- .5
constant c : signed(31 down to 0) := SIGNED(To_StdLogicVector(1110111001101011001010000000)); -- .25
constant d : signed(31 down to 0) := SIGNED(To_StdLogicVector(111011100110101100101000000)); -- .125
constant e : signed(31 down to 0) := SIGNED(To_StdLogicVector(11101110011010110010100000)); -- .0625
constant f : signed(31 down to 0) := SIGNED(To_StdLogicVector(1110111001101011001010000)); -- .03125
constant g : signed(31 down to 0) := SIGNED(To_StdLogicVector(111011100110101100101000)); -- .015625
constant h : signed(31 down to 0) := SIGNED(To_StdLogicVector(11101110011010110010100)); -- .0078125
constant i : signed(31 down to 0) := SIGNED(To_StdLogicVector(1110111001101011001010)); -- .00390625
constant j : signed(31 down to 0) := SIGNED(To_StdLogicVector(111011100110101100101)); -- .001953125
constant k : signed(31 down to 0) := SIGNED(To_StdLogicVector(11101110011010110010)); --.0009765625
constant l : signed(31 down to 0) := SIGNED(To_StdLogicVector(1110111001101011001)); -- .00048828125
constant m : signed(31 down to 0) := SIGNED(To_StdLogicVector(111011100110101100)); --.000244140625
constant n : signed(31 down to 0) := SIGNED(To_StdLogicVector(11101110011010110)); --.0001220703125
constant o : signed(31 down to 0) := SIGNED(To_StdLogicVector(1110111001101011)); --.00006103515625



PROCESS(clk)
begin
if z_in := 0 then x_out := x_in and y_out := y_in,
end if;

if z_in := a then z1 := a , and x_out := x_in - y_in*1*a, and y_out := y_in + x_in*1*a;
elseif Z_in > a then z1 := a + b, and x1 := x_in - y_in*1*z1, and y1 := y_in + x_in*1*z1,
elseif Z_in < a then z1 := a - b, and x1 := x_in - y_in*1*z1, and y1 := y_in + x_in*1*z1,
end if;

if Z_in := z1 then x_out := x_in - y_in*1*z1, and y_out := y_in + x_in*1*z1,
elseif z_in > z1 then z2 := z1 + c, and x2 := x1 - y1*1*z2, and y2 := y1 + x1*1*z2,
elseif z_in < z1 then z2 := z1 - c, and x2 := x1 - y1*1*z2, and y2 := y1 + x1*1*z2,
endif;

if z_in := z2 then x_out := x1 - y1*1*z2, and y_out := y1 + x1*1*z2,
elseif z_in > z2 then z3 := z2 + d, and x3 := x2 - y2*1*z3, and y3 := y2 + x2*1*z3,
elseif z_in < z2 then z3 := z2 - d, and x3 := x2 - y2*1*z3, and y3 := y2 + x2*1*z3,
endif;

if z_in := z3 then x_out := x2 - y2*1*z3, and y_out := y2 + x2*1*z3,
if z_in > z3 then z4 := z3 + e, and x_out := x3 - y3*1*z4, and y_out := y3 + x3*1*z4,
elseif z_in < z3 then z4 := z3 - e, and x_out := x_in - y_in*1*z4, and y_out := y_in + x_in*1*z4,
endif;

if z_in := z4 then x_out :=
if z_in > z4 then z5 := z4 + f, and x_out := x_in - y_in*1*z5, and y_out := y_in + x_in*1*z5,
elseif z_in < z4 then z5 := z4 - f, and x_out := x_in - y_in*1*z5, and y_out := y_in + x_in*1*z5,
endif;

if z_in > z5 then z6 := z5 + g, and x_out := x_in - y_in*1*z6, and y_out := y_in + x_in*1*z6,
elseif z_in < z5 then z6 := z5 - g, and x_out := x_in - y_in*1*z6, and y_out := y_in + x_in*1*z6,
endif;

if z_in > z6 then z7 := z6 + h, and x_out := x_in - y_in*1*z7, and y_out := y_in + x_in*1*z7,
elseif z_in < z6 then z7 := z6 - h, and x_out := x_in - y_in*1*z7, and y_out := y_in + x_in*1*z7,
endif;

if z_in > z7 then z8 := z7 + i, and x_out := x_in - y_in*1*z8, and y_out := y_in + x_in*1*z8,
elseif z_in < z7 then z8 := z7 - i, and x_out := x_in - y_in*1*z8, and y_out := y_in + x_in*1*z8,
endif;

if z_in > z8 then z9 := z8 + j, and x_out := x_in - y_in*1*z9, and y_out := y_in + x_in*1*z9,
elseif z_in < z8 then z9 := z8 - j, and x_out := x_in - y_in*1*z9, and y_out := y_in + x_in*1*z9,
endif;

if z_in > z9 then z10 := z9 + k, and x_out := x_in - y_in*1*z10, and y_out := y_in + x_in*1*z10,
elseif z_in < z9 then z10 := z9 - k, and x_out := x_in - y_in*1*z10, and y_out := y_in + x_in*1*z10,
endif;

if z_in > z10 then z11 := z10 + l, and x_out := x_in - y_in*1*z11, and y_out := y_in + x_in*1*z11,
elseif z_in < z10 then z11 := z10 - l, and x_out := x_in - y_in*1*z11, and y_out := y_in + x_in*1*z11,
endif;

if z_in > z11 then z12 := z11 + m, and x_out := x_in - y_in*1*z12, and y_out := y_in + x_in*1*z12,
elseif z_in < z11 then z12 := z11 - m, and x_out := x_in - y_in*1*z12, and y_out := y_in + x_in*1*z12,
endif;

if z_in > z12 then z13 := z12 + n, and x_out := x_in - y_in*1*z13, and y_out := y_in + x_in*1*z13,
elseif z_in < z12 then z12 := z12 - n, and x_out := x_in - y_in*1*z13, and y_out := y_in + x_in*1*z13,
endif;

if z_in > z13 then z14 := z13 + o, and x_out := x_in - y_in*1*z14, and y_out := y_in + x_in*1*z14,
elseif z_in < z13 then z14 := z13 - o, and x_out := x_in - y_in*1*z14, and y_out := y_in + x_in*1*z14,
endif;

 

[VHDLguy]

ouch. That is going to chew up the gates. Not to mention speed.. what speed do you plan on running this at?

Anyway,
As far as your constants go, I am not really sure what you are trying to do, but given that the to_stdlogicvector function only takes either a bit_vector or a std_ulogic_vector (unless you use std_logic_1164_extensions), then you problem is that you didn't put "'s around your bit vectors.


The other thing is that you will probably need to include 0's on the high end of your constants:

ie
constant a : unsigned(3 downto 0) := "1000"; -- correct
constant a : unsigned(5 downto 0) := "1000"; -- incorrect
constant a : unsigned(5 downto 0) := "001000"; -- correct

VHDL is so strongly typed that example 2 above will give you an error that left side is expecting 6 bits, right side is only 4 bits.

--

http://www.lateralsands.com/

 

[VHDLguy]

By the way, when I mentioned that I wasn't sure what you wre trying to do, what I meant was that your comments seem to suggest that you are trying to do floating point calculations, but your type is signed.

I don't tend to use signed (not in an indutry that requires much math in my designs, mainly bit manipulation), but as far as I understand they don't offer floating point arithmatic.

The other thing is that I didn't really pay close attention to your math, I guess you could be playing tricks to make a signed integer give you some required "floating point" answer??

--

http://www.lateralsands.com/

 

[philrivers]

Thanks very much for your help vhdl guy, it was much appreciated. I have since sorted out the issues with the architecture thanks to your help. However, I am unable to debug the remaining part of the code. I am not used to coding in vhdl and it looks fine to me. I have attched the code, and would appreciate any suggestions. Thanks in advance.


LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;



ENTITY cordic IS

PORT (
clk : IN STD_LOGIC;
load: IN STD_LOGIC;
res : IN STD_LOGIC;

x_in: IN STD_LOGIC_VECTOR(15 downto 0);
y_in: IN STD_LOGIC_VECTOR(15 downto 0);
z_in: IN STD_LOGIC_VECTOR(15 downto 0);

x_out: OUT STD_LOGIC_VECTOR(15 downto 0);
y_out: OUT STD_LOGIC_VECTOR(15 downto 0)

);

END cordic;

ARCHITECTURE cordic_arch OF cordic IS



constant K : signed(31 downto 0) := "00100100001100100000101001100011"; -- .607252935
constant a : signed(31 downto 0) := "00111011100110101100101000000000"; -- 1.0
constant b : signed(31 downto 0) := "00011101110011010110010100000000"; -- .5
constant c : signed(31 downto 0) := "00001110111001101011001010000000"; -- .25
constant d : signed(31 downto 0) := "00000111011100110101100101000000"; -- .125
constant e : signed(31 downto 0) := "00000011101110011010110010100000"; -- .0625
constant f : signed(31 downto 0) := "00000001110111001101011001010000"; -- .03125
constant g : signed(31 downto 0) := "00000000111011100110101100101000"; -- .015625
constant h : signed(31 downto 0) := "00000000011101110011010110010100"; -- .0078125
constant i : signed(31 downto 0) := "00000000001110111001101011001010"; -- .00390625
constant j : signed(31 downto 0) := "00000000000111011100110101100101"; -- .001953125
constant k : signed(31 downto 0) := "00000000000011101110011010110010"; --.0009765625
constant l : signed(31 downto 0) := "00000000000001110111001101011001"; -- .00048828125
constant m : signed(31 downto 0) := "00000000000000111011100110101100"; --.000244140625
constant n : signed(31 downto 0) := "00000000000000011101110011010110"; --.0001220703125
constant o : signed(31 downto 0) := "00000000000000001110111001101011"; --.00006103515625


begin PROCESS

PROCESS(clk)
begin
if z_in := 0 then x_out := x_in then y_out := y_in,
end if;

if z_in := a then z1 := a , x_out := x_in - y_in*1*a, y_out := y_in + x_in*1*a;
elseif Z_in > a then z1 := a + b, then x1 := x_in - y_in*1*z1, then y1 := y_in + x_in*1*z1,
elseif Z_in < a then z1 := a - b, then x1 := x_in - y_in*1*z1, then y1 := y_in + x_in*1*z1,
end if;

if Z_in := z1 then x_out := x_in - y_in*1*z1, then y_out := y_in + x_in*1*z1,
elseif z_in > z1 then z2 := z1 + c, then x2 := x1 - y1*1*z2, then y2 := y1 + x1*1*z2,
elseif z_in < z1 then z2 := z1 - c, then x2 := x1 - y1*1*z2, then y2 := y1 + x1*1*z2,
endif;

if z_in := z2 then x_out := x1 - y1*1*z2, then y_out := y1 + x1*1*z2,
elseif z_in > z2 then z3 := z2 + d, then x3 := x2 - y2*1*z3, then y3 := y2 + x2*1*z3,
elseif z_in < z2 then z3 := z2 - d, then x3 := x2 - y2*1*z3, then y3 := y2 + x2*1*z3,
endif;

if z_in := z3 then x_out := x2 - y2*1*z3, then y_out := y2 + x2*1*z3,
if z_in > z3 then z4 := z3 + e, then x_out := x3 - y3*1*z4, then y_out := y3 + x3*1*z4,
elseif z_in < z3 then z4 := z3 - e, then x_out := x_in - y_in*1*z4, then y_out := y_in + x_in*1*z4,
endif;

if z_in := z4 then x_out :=
if z_in > z4 then z5 := z4 + f, then x_out := x_in - y_in*1*z5, then y_out := y_in + x_in*1*z5,
elseif z_in < z4 then z5 := z4 - f, then x_out := x_in - y_in*1*z5, then y_out := y_in + x_in*1*z5,
endif;

if z_in > z5 then z6 := z5 + g, then x_out := x_in - y_in*1*z6, then y_out := y_in + x_in*1*z6,
elseif z_in < z5 then z6 := z5 - g, then x_out := x_in - y_in*1*z6, then y_out := y_in + x_in*1*z6,
endif;

if z_in > z6 then z7 := z6 + h, then x_out := x_in - y_in*1*z7, then y_out := y_in + x_in*1*z7,
elseif z_in < z6 then z7 := z6 - h, then x_out := x_in - y_in*1*z7, then y_out := y_in + x_in*1*z7,
endif;

if z_in > z7 then z8 := z7 + i, then x_out := x_in - y_in*1*z8, then y_out := y_in + x_in*1*z8,
elseif z_in < z7 then z8 := z7 - i, then x_out := x_in - y_in*1*z8, then y_out := y_in + x_in*1*z8,
endif;

if z_in > z8 then z9 := z8 + j, then x_out := x_in - y_in*1*z9, then y_out := y_in + x_in*1*z9,
elseif z_in < z8 then z9 := z8 - j, then x_out := x_in - y_in*1*z9, then y_out := y_in + x_in*1*z9,
endif;

if z_in > z9 then z10 := z9 + k, then x_out := x_in - y_in*1*z10, then y_out := y_in + x_in*1*z10,
elseif z_in < z9 then z10 := z9 - k, then x_out := x_in - y_in*1*z10, then y_out := y_in + x_in*1*z10,
endif;

if z_in > z10 then z11 := z10 + l, then x_out := x_in - y_in*1*z11, then y_out := y_in + x_in*1*z11,
elseif z_in < z10 then z11 := z10 - l, then x_out := x_in - y_in*1*z11, then y_out := y_in + x_in*1*z11,
endif;

if z_in > z11 then z12 := z11 + m, then x_out := x_in - y_in*1*z12, then y_out := y_in + x_in*1*z12,
elseif z_in < z11 then z12 := z11 - m, then x_out := x_in - y_in*1*z12, then y_out := y_in + x_in*1*z12,
endif;

if z_in > z12 then z13 := z12 + n, then x_out := x_in - y_in*1*z13, then y_out := y_in + x_in*1*z13,
elseif z_in < z12 then z12 := z12 - n, then x_out := x_in - y_in*1*z13, then y_out := y_in + x_in*1*z13,
endif;

if z_in > z13 then z14 := z13 + o, then x_out := x_in - y_in*1*z14, then y_out := y_in + x_in*1*z14,
elseif z_in < z13 then z14 := z13 - o, then x_out := x_in - y_in*1*z14, then y_out := y_in + x_in*1*z14,
endif;






end PROCESS;

 

[VHDLguy]

any error messages?

--

http://www.lateralsands.com/

 

[VHDLguy]

hmmm taking a closer look, there are probably lots of error messages.

the first thing that jumps out is the you are using the variable assigment rather than the signal assignment.

:= should only be used for variables.
<= should be used for signals.

Secondly, I am unsure about your "if then" usage. Maybe its something you can do, but I have never seen it before.

Oh, and conditional statements don't use : (or < unless its a less than operator) just = or /= (not equal) <, >, <=, >=


so your first line:
if z_in := 0 then x_out := x_in then y_out := y_in,

I would write as:
if (z_in = 0) then
x_out <= x_in;
y_out <= y_in;
end if;

try that for starters.

--

http://www.lateralsands.com/

 

[VHDLguy]

ooops. I also forgot to mention that you must match types ALWAYS.

For example the if statement i mentioned above is incorrect unles z_in is of type integer.

rather you should write either
if z_in = "0000000000000000" then

or you should create a constant equal to "0000000000000000" of type std_logic_vector(15 downto 0) and say:
if z_in = zeros_15 then

or you can use a conversion routine:
if z_in = to_stdlogicvector(bit_vector'(X"0000")) then

if you look in std_logic_1164 you will see that to_stdlogicvector can convert from bit_vector to std_logic_vector. X"0000" is hex 0000 (16 bits) in bit_string format, so with a type cast to bit_vector the conversion works.

you could also use conv_std_logic_vector from the std_logic_arith package. One of its possible uses is with two integer inputs conv_std_logic_vector(0, 16) (value = 0, number of bits = 16)

if z_in = conv_std_logic_vector(0,16) then


Finally. Just to add some more to what I have already said. Since you are declaring std_logic_arith which includes the type unsigned and signed, you will need to type cast any vector which could be interpreted as unsigned, signed, or std_logic_vector.

So my example of
if z_in = "0000000000000000" then

would not work since "0000000000000000" could be any of the mentioned types.

you should rather write that as
if z_in = std_logic_vector'("0000000000000000") then


--

http://www.lateralsands.com/

 

[philrivers]

Hi, many thnks for all your help, i reckon I owe you a coupla pints. Essentially im nearly done. I think that youve sorta realised what im trying to do. Anyway the remaining errors are to do with match up problems between expected sizes of results and actual sizes. Would there be any easy resolution to this other than me working them out,ie is there any way of getting the code make it realise just to put in sufficient 0's to make up the space?

on another note but as side issues not really important as errors, would it be possible to have small upper and lower bounded limits for my constants,e.g. if the constant(that gets compared with) was 7 would i be able to code it to accept say 7.05?
oh and would there be a good way of picking the most close answer out of the 15 or so if none proved to be completely right. could this be by storing the results somewhere?
again, many thanks

LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;



ENTITY cordic IS

PORT (
clk : IN STD_LOGIC;
load: IN STD_LOGIC;
res : IN STD_LOGIC;

x_in: IN STD_LOGIC_VECTOR(31 downto 0);
y_in: IN STD_LOGIC_VECTOR(31 downto 0);
z_in: IN STD_LOGIC_VECTOR(31 downto 0);

x_out: OUT STD_LOGIC_VECTOR(64 downto 0);
y_out: OUT STD_LOGIC_VECTOR(64 downto 0)

);

END cordic;

ARCHITECTURE cordic_arch OF cordic IS

SIGNAL x1 : STD_LOGIC_VECTOR (64 downto 0);
SIGNAL x2 : STD_LOGIC_VECTOR (97 downto 0);
SIGNAL x3 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x4 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x5 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x6 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x7 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x8 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x9 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x10 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x11 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x12 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x13 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL x14 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y1 : STD_LOGIC_VECTOR (64 downto 0);
SIGNAL y2 : STD_LOGIC_VECTOR (97 downto 0);
SIGNAL y3 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y4 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y5 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y6 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y7 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y8 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y9 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y10 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y11 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y12 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y13 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL y14 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z1 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z2 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z3 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z4 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z5 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z6 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z7 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z8 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z9 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z10 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z11 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z12 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z13 : STD_LOGIC_VECTOR (31 downto 0);
SIGNAL z14 : STD_LOGIC_VECTOR (31 downto 0);
constant Q : STD_LOGIC_VECTOR(31 downto 0) := "00100100001100100000101001100011"; -- .607252935 operator K
constant a : STD_LOGIC_VECTOR(31 downto 0) := "00111011100110101100101000000000"; -- 1.0
constant b : STD_LOGIC_VECTOR(31 downto 0) := "00011101110011010110010100000000"; -- .5
constant c : STD_LOGIC_VECTOR(31 downto 0) := "00001110111001101011001010000000"; -- .25
constant d : STD_LOGIC_VECTOR(31 downto 0) := "00000111011100110101100101000000"; -- .125
constant e : STD_LOGIC_VECTOR(31 downto 0) := "00000011101110011010110010100000"; -- .0625
constant f : STD_LOGIC_VECTOR(31 downto 0) := "00000001110111001101011001010000"; -- .03125
constant g : STD_LOGIC_VECTOR(31 downto 0) := "00000000111011100110101100101000"; -- .015625
constant h : STD_LOGIC_VECTOR(31 downto 0) := "00000000011101110011010110010100"; -- .0078125
constant i : STD_LOGIC_VECTOR(31 downto 0) := "00000000001110111001101011001010"; -- .00390625
constant j : STD_LOGIC_VECTOR(31 downto 0) := "00000000000111011100110101100101"; -- .001953125
constant k : STD_LOGIC_VECTOR(31 downto 0) := "00000000000011101110011010110010"; --.0009765625
constant l : STD_LOGIC_VECTOR(31 downto 0) := "00000000000001110111001101011001"; -- .00048828125
constant m : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000111011100110101100"; --.000244140625
constant n : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000011101110011010110"; --.0001220703125
constant o : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000001110111001101011"; --.00006103515625


begin


PROCESS(clk)

begin
if (z_in = 0) then
x_out <= x_in;
y_out <= y_in;
end if;



if
z_in = a then
z1 <= a ;
x_out <= x_in - y_in*"1"*a;
y_out <= y_in + x_in*"1"*a;
else
if
(Z_in > a) then
z1 <= a + b;
x1 <= x_in - y_in*"1"*z1;
y1 <= y_in + x_in*"1"*z1;
else
if (Z_in < a) then
z1 <= a - b;
x1 <= x_in - y_in*"1"*z1;
y1 <= y_in + x_in*"1"*z1;
end if;
end if;
end if;
if (Z_in = z1) then
x_out <= x_in - y_in*"1"*z1;
y_out <= y_in + x_in*"1"*z1;
else
if (z_in > z1) then
z2 <= z1 + c;
x2 <= x1 - y1*"1"*z2;
y2 <= y1 + x1*"1"*z2;
else
if (z_in < z1) then
z2 <= z1 - c;
x2 <= x1 - y1*"1"*z2;
y2 <= y1 + x1*"1"*z2;
end if;
end if;
end if;
if (z_in = z2) then
x_out <= x1 - y1*"1"*z2;
y_out <= y1 + x1*"1"*z2;
else
if (z_in > z2) then
z3 <= z2 + d;
x3 <= x2 - y2*"1"*z3;
y3 <= y2 + x2*"1"*z3;
else
if (z_in < z2) then
z3 <= z2 - d;
x3 <= x2 - y2*"1"*z3;
y3 <= y2 + x2*"1"*z3;

end if;
end if;
end if;
if (z_in = z3) then
x_out <= x2 - y2*"1"*z3;
y_out <= y2 + x2*"1"*z3;
else
if (z_in > z3) then
z4 <= z3 + e;
x_out <= x3 - y3*"1"*z4;
y_out <= y3 + x3*"1"*z4;
else
if (z_in < z3) then
z4 <= z3 - e;
x_out <= x3 - y3*"1"*z4;
y_out <= y3 + x3*"1"*z4;

end if;
end if;
end if;
if (z_in = z4) then
x_out <= x3 - y3*"1"*z4;
y_out <= y3 - x3*"1"*z4;
else
if (z_in > z4) then
z5 <= z4 + f;
x_out <= x4 - y4*"1"*z5;
y_out <= y4 + x4*"1"*z5;
else
if (z_in < z4) then
z5 <= z4 - f;
x_out <= x4 - y4*"1"*z5;
y_out <= y4 + x4*"1"*z5;

end if;
end if;
end if;
if (z_in = z5) then
x_out <= x4 - y4*"1"*z5;
y_out <= y4 - x4*"1"*z5;
else
if (z_in > z5) then
z6 <= z5 + g;
x_out <= x5 - y5*"1"*z6;
y_out <= y5 + x5*"1"*z6;
else
if (z_in < z5) then
z6 <= z5 - g;
x_out <= x5 - y5*"1"*z6;
y_out <= y5 + x5*"1"*z6;

end if;
end if;
end if;

if (z_in = z6) then
x_out <= x5 - y5*"1"*z6;
y_out <= y5 - x5*"1"*z6;
else
if (z_in > z6) then
z7 <= z6 + h;
x_out <= x6 - y6*"1"*z7;
y_out <= y6 + x6*"1"*z7;
else
if z_in < z6 then
z7 <= z6 - h;
x_out <= x6 - y6*"1"*z7;
y_out <= y6 + x6*"1"*z7;
end if;
end if;
end if;
if (z_in = z7) then
x_out <= x6 - y6*"1"*z7;
y_out <= y6 - x6*"1"*z7;
else
if (z_in > z7) then
z8 <= z7 + i;
x_out <= x7 - y7*"1"*z8;
y_out <= y7 + x7*"1"*z8;
else
if (z_in < z7) then
z8 <= z7 - i;
x_out <= x7 - y7*"1"*z8;
y_out <= y7 + x7*"1"*z8;

end if;
end if;
end if;
if (z_in = z8) then
x_out <= x7 - y7*"1"*z8;
y_out <= y7 - x7*"1"*z8;
else
if (z_in > z8) then
z9 <= z8 + j;
x_out <= x8 - y8*"1"*z9;
y_out <= y8 + x8*"1"*z9;
else
if (z_in < z8) then
z9 <= z8 - j;
x_out <= x8 - y8*"1"*z9;
y_out <= y8 + x8*"1"*z9;
end if;
end if;
end if;
if (z_in = z9) then
x_out <= x8 - y8*"1"*z9;
y_out <= y8 - x8*"1"*z9;
else
if (z_in > z9) then
z10 <= z9 + k;
x_out <= x9 - y9*"1"*z10;
y_out <= y9 + x9*"1"*z10;
else
if (z_in < z9) then
z10 <= z9 - k;
x_out <= x9 - y9*"1"*z10;
y_out <= y9 + x9*"1"*z10;
end if;
end if;
end if;


if (z_in = z10) then
x_out <= x9 - y9*"1"*z10;
y_out <= y9 - x9*"1"*z10;
else
if (z_in > z10) then
z11 <= z10 + l;
x_out <= x10 - y10*"1"*z11;
y_out <= y10 + x10*"1"*z11;
else
if (z_in < z10) then
z11 <= z10 - l;
x_out <= x10 - y10*"1"*z11;
y_out <= y10 + x10*"1"*z11;
else
end if;
end if;
end if;
if (z_in = z11) then
x_out <= x10 - y10*"1"*z11;
y_out <= y10 - x10*"1"*z11;
else
if (z_in > z11) then
z12 <= z11 + m;
x_out <= x11 - y11*"1"*z12;
y_out <= y11 + x11*"1"*z12;
else
if (z_in < z11) then
z12 <= z11 - m;
x_out <= x11 - y11*"1"*z12;
y_out <= y11 + x11*"1"*z12;
end if;
end if;
end if;
if (z_in = z12) then
x_out <= x11 - y11*"1"*z12;
y_out <= y11 - x11*"1"*z12;
else
if (z_in > z12) then
z13 <= z12 + n;
x_out <= x12 - y12*"1"*z13;
y_out <= y12 + x12*"1"*z13;
else
if (z_in < z12) then
z13 <= z12 - n;
x_out <= x12 - y12*"1"*z13;
y_out <= y12 + x12*"1"*z13;
end if;
end if;
end if;
if (z_in = z13) then
x_out <= x12 - y12*"1"*z13;
y_out <= y12 - x12*"1"*z13;
else
if (z_in > z13) then
z14 <= z13 + o;
x_out <= x13 - y13*"1"*z14;
y_out <= y13 + x13*"1"*z14;
else
if (z_in < z13) then
z14 <= z13 - o;
x_out <= x13 - y13*"1"*z14;
y_out <= y13 + x13*"1"*z14;
end if;
end if;
end if;








end PROCESS;

end cordic_arch;

 

[VHDLguy]

As far as putting in the extra 0's goes... you could probably do it using a conversion routine.

for example say you want to put 10010 into a std_logic_vector(31 downto 0). Find an appropriate converions routine to convert from integer to slv or something similar and then you can simply use the integer value of 18 or a hex value of 0x12.

For example:
to_stdlogicvector(bit_vector'(X"12")) convert hex 12 from bit array to bit_vector, and then from bit_vector to slv.
the problem with that method is that you must match your hex value to the size of your slv (in the above case it would only work for 8 bits). this requires ieee.std_logic_1164 package

another method might be:
conv_std_logic_vector(18,32)
convert integer 18 to a 32bit slv. Requires ieee.std_logic_arith package


You 7.05 question I don't fully understand. but ignoring my not completely understanding how this works... you could have another constant with your margin of .05 (or whatever). then have two more signals one that is your value plus that margin, the other your value minus the margin, then compare to see if you are within the two (greater than one, less than the other).

And for your checking to see what constant you are closest too. I imagine in this instance, counting the number of leading 0's would tell you what you are closest too. then you might need to do some subtraction to test the two surrounding values to see if you are past the halfway point or what.

ie.if bits 31-27 = "00001" then you are going to be close to c. So first compare with c, if less than c then you need to compare c and d to see who is closest, if greater than c then compare c and b to see who is closest.

to do that easily you could create an array type and assign the constants to the array based on the number of leading zeros. that way you can count the zero's in a for loop, then use the result to access the constants. if you just assign the constants to the array after the begin in your architecture (ie not in a process) then it won't use up any more logic (apart for the mux for selecting the right values - you would probably need more if statements than that to go through each value and compare one by one anyway).

let me know if thats not clear.

--

http://www.lateralsands.com/