I have some error that cannot fix:

[whizmummy]

I have some error that cannot fix:
1. set on less than
2. cannot assign A,B for test purpose
Here is my code>>>>
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity ALU is
port (
A, B: in BIT_VECTOR(3 downto 0);
OP: in BIT_VECTOR(2 downto 0);
CLK: in BIT;
F: buffer BIT_VECTOR(3 downto 0));
end ALU;

architecture BEHAVIORAL of ALU is
begin
process(CLK,OP)
A := "0101"; -- Assign A = 5 for test purpose
B := "0111"; -- B = 7
begin
if (CLK'EVENT and CLK = '1') then
case OP is
when &quot;000&quot; => F <= (A + B); -- Add
when &quot;001&quot; => F <= A + (NOT B); -- Sub
when &quot;010&quot; => F <= A and B; -- And
when &quot;011&quot; => F <= A or B; -- Or
when &quot;100&quot; => F <= A sll 1; -- Shift left logical
when &quot;101&quot; => F <= A srl 1; -- Shift right logical
when &quot;111&quot; => F <= &quot;0001&quot; when (A < B) else &quot;000&quot;; -- set on less than
when others => F <= F;
end case;
end if;
end process;
end BEHAVIORAL;

 

[ahedin]

You can use default values for inputs.
Sometimes it helps to only have one input per line.

entity ALU is
port (
A : in BIT_VECTOR(3 downto 0) := 5;
B: in BIT_VECTOR(3 downto 0) := 7;
OP: in BIT_VECTOR(2 downto 0);
CLK: in BIT;
F: buffer BIT_VECTOR(3 downto 0));
end ALU;

A and B are signals so use <= to assign them a value. The := operator is variables, constants, and default values.

The area after process() and before begin is for declaring variables. You must do assignment statements after the 'begin'.

The set on less than needs to be written another way.
The F <= &quot;0001&quot; when (A < B) else &quot;000&quot;; statement cannot be used in a sequential data flow area.

if (A < B) then
F <= &quot;0001&quot;;
else
F <= &quot;0000&quot;;
end if;

 

[whizmummy]

Thanks a lot, ahedin.