bigguyhawaii
Vendor
i have a cs1000e 6.0 ha system with 3 pri tmdi cards.
loops 40,41,42 with the first 2 in mg 4.0 and the third
in mg 8.0. i have clock cards on 40 and 42. 40 is pref to itself 4 0 3 and spref to 4 0 4 (lp41). the other clock controller card is on 8 0 3 with no settings for prim or secondary reference. i've tried to pref to 8 0 3 on the 2nd clock controller but i get a error that the prim has to match the slot number of the clock controller. i will put the secondary in freerun since this is the only span in this mg. i assume that i need one just in case i lose the other span(s). so that the switch won't run in freerun.
REQ prt
TYPE ddb
MGCLK 4 0 3
PREF 4 0 3
SREF 4 0 4
MGCLK 8 0 3
PREF
SREF
TRSH 00
RALM 128
BIPC 2
LFAC 3
BIPV 4 4
SRTK 24 3600
SRNT 1024 1024
LFAL 10240 10240
SRIM 1
SRMM 2
ICS
loops 40,41,42 with the first 2 in mg 4.0 and the third
in mg 8.0. i have clock cards on 40 and 42. 40 is pref to itself 4 0 3 and spref to 4 0 4 (lp41). the other clock controller card is on 8 0 3 with no settings for prim or secondary reference. i've tried to pref to 8 0 3 on the 2nd clock controller but i get a error that the prim has to match the slot number of the clock controller. i will put the secondary in freerun since this is the only span in this mg. i assume that i need one just in case i lose the other span(s). so that the switch won't run in freerun.
REQ prt
TYPE ddb
MGCLK 4 0 3
PREF 4 0 3
SREF 4 0 4
MGCLK 8 0 3
PREF
SREF
TRSH 00
RALM 128
BIPC 2
LFAC 3
BIPV 4 4
SRTK 24 3600
SRNT 1024 1024
LFAL 10240 10240
SRIM 1
SRMM 2
ICS