How to implement a 2-way buffer based on a signal

[wilchang]

I'm not sure if this would be possible to code in VHDL, but I would like to implement a two-way buffer using a CPLD (Complex Programmable Logic Device) where the input signal OE (OutputEnable) would determine the direction of the output.

So would it be possible to have two std_logic_vector's, say A and B, have their input and output determined based on a std_logic input signal OE?

So for example, if OE was high, then A would be the input, and B would be the output. Then if OE was low, then A would be the output, and B would be the input.

I can get this to work in ABEL HDL with INOUT signals but I can't seem to wrap my mind around how to approach this correctly in VHDL.

Thanks!

 

[jeandelfrigo]

wildchang,

This is perfectly possible in VHDL.

lets say the inout port is named A
A_int is an internal signal containing the output values for the port
A_OE is the output enable for the port A


you use the following syntax to asign the output:

A <= A_int when A_OE = '1' else 'Z';

This is for a standard logic;

For a vector this would be:

A <= A_int when A_OE = '1' else (others => 'Z');

You can at all times use A as an input, it's just for the output usage that you need to be sure no other device is driving the port.

The synthesizer will recognize the above code lines and instantiate tristate IO buffers. Most CPLDs I know have these.

Another way is checking the CPLD vendor documentation and instantiating the tristate IO buffer primitives directly from your VHDL. (Use generate for loops for vectors).

regards,

Jeandelfrigo