how can i determine the frequency of a clock output?

[spidermanvenom]

Hallo everyone,

I'm doing my project about camera link, and i need to know the code on how to determine the frequency of a clock. the output of the camera goes to the ALTERA PLD.


Thanks!

c",)-

 

[VHDLguy]

Im not sure I understand.

Do you have a clock input to the PLD and you would like to try and figure out what speed that clock is?
- short answer here is that you need a faster clock to sample and count (at the faster clock rate) how long between each change in the slower clock. The faster the clock the less sampling error.

Or are you asking, how do I produce a clock of frequency X.
- You must have a clock source, then use a PLL (DCM) to re-generate another frequency based on the original clock.

Or, are you asking, at what maximum speed will my code work at worst condition?
- After synthesis the tool wil show worst paths. Worst case path is the maximum frequency that your code (with the current synthesis, place and route etc) will run at without any errors occuring.

--

http://www.lateralsands.com/

 

[spidermanvenom]

Thank you for the reply.

I need to know the speed of the input clock to the PLD and my problem is I don't know how to count it. I need to divide the clock pulse width into 7 bits. From that, I will get the input data in every bit of it. I don't know how can I implement it in VHDL.

Thanks again and best regards.

 

[VHDLguy]

7 bits as in 7 samples?

or 7 bits as in 2^7 = 128 samples?

In either case you are going to need to have another clock that is 7 or 128 times the speed of the clock that you are counting.

Unless you can somehow do it in combinatorial gates, but nothing springs to mind.

 

[spidermanvenom]

sorry for that, i mean 7 samples only. i'm studying now about pll and LVDS receiver. I hope this will help me but I can't find VHDL file for pll. Thanks!

 

[VHDLguy]

You won't find any VHDL specifically for creating a PLL. It will be some hardware included in a FPGA that you just need to add en entity for.

In a Xilinx FPGA you would use the Architecture Wizard and choose a DCM. You can then add in the requirements you wish. There is something similar in Altera software, but I forget what it is called.

They both create an entity in VHDL that you simply place into your code and hook up as required.

--

http://www.lateralsands.com/

 

[spidermanvenom]

Thank you for you reply VHDLGuy. I look at the altera's function components and unfortunately the family device I am using does not support PLL components that's why I'm looking a VHDL code for it...

Thanks.....

 

[VHDLguy]

Im not strong on PLL's but I think you will find that you cannot implement anything that you require in VHDL. A PLL is analog, so nothing going there.

On the other hand there is a DLL or Delay Locked Loop, I am not really sure how they are implemented but they are called digital, so I guess it could be at least modeled in VHDL. My guess is that you need MUCH tighter place and route control than you can possibly implement in an FPGA.

Your better bet is to have an external PLL to multiply your clock. Even if you have to output the clock, then have another input with a faster clock, you will get better results .

Anyway:
You are trying to figure out the speed of a clock. You can't just speed up that same clock by 7 times, you will need a fixed clock that you know the speed of, and then use that to figure out the speed of the other clock. You are saying that you only require an accuracy of 1/7th of the actual clock speed (well you didn't say that - I said that based on your requirement of 7 samples), in which case you need an external clock of at least 7 times your maximum clock speed.

The next question is... do you really need to know the frequency? Why?

--

http://www.lateralsands.com/

 

[spidermanvenom]

I really don't need to know the frequency, it's just my idea on how I can generate a clock that is 1/7 of the input clock. On my case, I don't have to use any external clock signals, only the input clock signal is my reference. Everything should be written in VHDL, that's why I'm studying about DPLL. I already did a VHDL program that generates fast clock but unfortunately I due to some problems (I don't know why), some VHDL sequential synthax like "WAIT FOR" or even "IF GENERATE" statements did not works on my compiler. As of now, I really don't have an idea how to implement it. I already search for it on the web but still I can't find an answer on my problem. I guess, another problem is the limitations of the PLD and the compiler I am using.


Thanks again!

 

[VHDLguy]

When you say "Wait for" did not work on my compiler, are you talking about a simulator or a synthesizer? Because a "wait for 10ns" or anything like that will never work on a synthesizer, its just not something you can do in digital logic. It exists only for behavioural models.

So, your final goal is to create a slower clock than the input? at 1/7th the speed?

If so then it is quite simple, simply count clocks and invert your new clock at the appropriate time. If you need 1/7th and 50/50 duty cycle then its a bit more difficult because you need to deal with rising and falling edges. Or if its ok you could just count 3 clocks then 4 clocks so you would end up with a 3/7th - 4/7th duty cycle (or 42/58).

But if your goal is a faster clock (not 1/7 but 7x) then a PLL is your only option.

--

http://www.lateralsands.com/

 

[spidermanvenom]

Maybe that my mistake, I do not understand yet the difference between synthesizer and simulator. What I mean is I need a clock with a period of 1/7 of the input clock. I think it's not 7x coz if I will make it 7x, time will come that it will not synchronize with the input clock.

Thanks again!

 

[VHDLguy]

A simulator is something like Modelsim that you can compile your design and testbench and view what happens to the signals on a waveform on your PC.

The synthesizer creates the netlist and bitmap files that you program your PLD/FPGA with.

Any VHDL is valid for a simulator, but only a sub-set of VHDL can be used for synthesizing. Anything that doesn't describe digital logic cannot be written in synthesizable logic (or RTL).

for example this is not synthesizable, but if you were in a hurry you could conceivably do it in a testbench:
A <= '1';
wait for 10 ns;
A <= '0';
wait for 20 ns;
A <= '1';
wait for 10 ns;
A <= '0';
wait for 20 ns;


If you were to describe something like the above in RTL you would need a 100Mhz clock and one way to do it would be something like:
signal A : std_logic;
signal cnt : std_logic_vector(1 downto 0);

[ .. snip .. ]

-- asynchronous reset
if rst = '1' then
A <= '1';
cnt <= &quot;00&quot;;
-- clock - rising edge
elsif clk'event and clk = '1' then
if (cnt = &quot;01&quot; and A = '1') then
A <= not A;
cnt <= &quot;00&quot;;
elsif (cnt = &quot;10&quot and A = '0') then
A <= not A;
cnt <= &quot;00&quot;;
else
cnt <= cnt + 1;
end if;
end if;

Note that I tend to use unsigned rather than std_logic_vector, I forget off the top of my head if I can do cnt <= cnt + 1 or if I need to do some conversions first.

--

http://www.lateralsands.com/

 

[spidermanvenom]

Sorry for the late reply.
Anyway, Thanks for the information. This forum helps me a lot. Thanks again!