Hi, Is it correct to have a sign 1

[RVSachin]

Hi,

Is it correct to have a signal in the sensitivity list of a process just because it appears on the RHS of an assignment even though the same signal is also on the LHS?

Consider the following example:

process(en, b)
begin
if en = '1' then
a(0) <= a(0) and b(1);
-- other assignments
else
a(0) <= a(0) or b(1);
-- other assignments
end if;
end process;

In this case, is it really necessary to have a (.. or a(0) ) in the sensitivity list just because a(0) is one of the inputs. By having 'a' in the sensitivity list, aren't we forcing the process to execute infinetely?

-RV

 

[berett]

The general response is yes - the sensitivity list must contain all the signals from the &quot;right side&quot; ,the conditions etc. (excluding the clocked processes where only the clock and optionally reset is required).

Concerning the code presented - it is unusual. It is not common practice to make the closed loops of combinatorial logic. If your target is the sequential logic you shall do it in another way.

Eventually if the simulator breaks down because of the sensitivity list then it means that the code is &quot;wrong&quot;, not acceptable from technical point of view etc.

Just imagine - from hardware point of view - what happens if you connect the output of the and gate to the input ...
in digital domain there may be no stable result of the operation i.e you get a kind of generator - the analogue chip.

Such loops are reasonable only with the flip-flop placed somewhere on the way of cirulating signal.

btw what is your target?

 

[RVSachin]

Thanks for the explanation.

I was just wondering about the VHDL LRM about the sensitivity lists and what is right/wrong in cases like the one mentioned above.