Hi all. In part of my code, I ha

[naraic]

Hi all.

In part of my code, I have the following

val <= &quot;1010&quot; when input(9) = '1' else
    &quot;1001&quot; when input(8) = '1' else
    &quot;1000&quot; when input(7) = '1' else
    &quot;0111&quot; when input(6) = '1' else
    &quot;0110&quot; when input(5) = '1' else
    &quot;0101&quot; when input(4) = '1' else
    &quot;0100&quot; when input(3) = '1' else
    &quot;0011&quot; when input(2) = '1' else
    &quot;0010&quot; when input(1) = '1' else
    &quot;0001&quot; when input(0) = '1' else
    &quot;0000&quot;;

This performs the same functionality as

val <= &quot;1010&quot; when input = &quot;1---------&quot; else
    &quot;1001&quot; when input = &quot;01--------&quot; else
    &quot;1000&quot; when input = &quot;001-------&quot; else
    &quot;0111&quot; when input = &quot;0001------&quot; else
    &quot;0110&quot; when input = &quot;00001-----&quot; else
    &quot;0101&quot; when input = &quot;000001----&quot; else
    &quot;0100&quot; when input = &quot;0000001---&quot; else
    &quot;0011&quot; when input = &quot;00000001--&quot; else
    &quot;0010&quot; when input = &quot;000000001-&quot; else
    &quot;0001&quot; when input = &quot;0000000001&quot; else
    &quot;0000&quot;; --when input = &quot;0000000000&quot;;

val is a 4-bit

std_logic_vector

and input is an 11-bit

std_logic_vector

. When I synthesise it, I get timing violations, and if I run the post-place&route simulation, I get some 'X's in val.

Is there any way this can be made more efficient, either by use of different vhdl, or by changing the logic of it?

Thanks

Ciaran

 

[berett]

The coding (1-st version) is OK generally. But this may be done by various kinds of hardware. This could be e.g. riddiculously long cascade of MUXes. Slow. And seems like this is the case here - you get time violations.
Another solution is the single mux with more complicated logic. Faster.

Seems all strange, as usually the time constraints force the the synthesizer to take faster solution.

Regardless of what the reason is you can write it in another way, forcing 1 mux (I mean no more cascades but with explicitly more complicated control logic). E.g.

val <= &quot;1010&quot;
when input = &quot;1000000000&quot; or input = &quot;1111111111&quot; else
&quot;1001&quot;
when input = &quot;0100000000&quot; or input = &quot;0111111111&quot; else

e.t.c.

... and pray that the synthesizer does not try to &quot;optimise&quot; it back to the cascade solution ...

optionally you can try to write it in the original way
but using process with if - else. The same functionality, but may engage different procedures from the synthesis software. If this one helped particularly I would very appreciate the feedback !

good luck !

 

[naraic]

I fixed the problem by using logic gates

e.g.

val[3] <= input(9) or input(8) or input(7);

val[2]

,

val[1]

and

val[0]

got more complex, but it fixed the timing problems.

I don't know, is it better to use logic gates than select statements?

Ciarán

 

[VHDLguy]

If you are really looking for speed then the best bet is to go for something that the synthesizer can only do &quot;one&quot; way (a way that you have decided is fast). I say &quot;one&quot; with quotes because it may make some optimization, but at least you know it will implement it in a particular way (ie with logic gates in this case, no mux'es etc).

In this case logic gates are possibly the best way. Your code might be a little long but the only thing the synthesizer might do is put your logic into a Karnaugh map and create a little better implementation using simple logic gates.

Personally I would avoid these kinds of implementations because of unreadability (ie 1 year later you can't remember your exact intention) and ease of mistakes. But in some situations the speed requires it. I often implement something in a readable fashion, then comment it out, and rewrite it.... that way the commented out version is kind of a comment on what I was trying to do.

--

http://www.lateralsands.com/

 

[naraic]

That's where good documentation comes in. It's a shame not to implement the faster option because of readability (especially in a language like VHDL). I tend to use comments within the code to fully document all that is going on.