got Latch for next_state in FSM, VHDL, please help!

[darthcheng]

I got a problem for my FSM, Xilinx ISE always found latch for my next_state signal in my FSM, and the next_state signal been recognized as a clock signal!! I have cover every case and every else, but it just the same, why??????Here is the code:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- for conv_std_logic_vector
use ieee.std_logic_unsigned.all; -- for conv_integer

entity CSMA_CA_controller is
port(
CLK : in std_logic;
en : in std_logic;
reset : in std_logic;
random_delay_done : in std_logic;
beacon_period : in std_logic;
backoff_period_boundary : in std_logic;
CCA_result : in std_logic_vector(1 downto 0);
packet_length : in std_logic_vector(7 downto 0);
counter_Backoff_period : in std_logic_vector(19 downto 0);
random_delay_en : out std_logic;
random_delay_pause : out std_logic;
CCA_en : out std_logic;
CSMA_CA_result : out std_logic_vector(1 downto 0);
random_delay_BE : out std_logic_vector(2 downto 0));
end CSMA_CA_controller;

architecture behavior of CSMA_CA_controller is
type state_type is (A, B, C, D, E, Failure, Success);
signal present_state, next_state : state_type;

begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if reset = '1' or en = '0' then
present_state <= A;
else
present_state <= next_state;
end if;
else null;
end if;
end process;

process(present_state, backoff_period_boundary, beacon_period, random_delay_done, counter_Backoff_period, packet_length, CCA_result)
constant symbol : integer := 128; -- one symbol period equal to 128 clock cycles
constant UBT : integer := 20; -- aUnitBackoffTime in symbols
constant BSD : integer := 960; -- aBaseSuperframeDuration in symbols
constant BO : integer := 1; -- macBeaconOrder, range from 0 to 14
constant macMinBE : integer := 2; -- minimum value of the backoff exponent
constant aMaxBE : integer := 5; -- the maximum value of the backoff exponent in the CSMA-CA algorithm
constant macMaxCSMABackoffs : integer := 4; -- the maximum number of backoffs

variable NB : integer range 0 to 7; -- number of times of backoff
variable CW : integer range 0 to 2; -- contention window length
variable BE : integer range 0 to 6; -- backoff exponent

begin
random_delay_en <= '0';
random_delay_pause <= '0';
random_delay_BE <= "000";
CCA_en <= '0';
CSMA_CA_result <= "00";

case present_state is

when A =>
NB := 0;
CW := 2;
BE := 2;

if backoff_period_boundary = '1' then
next_state <= B;
else
next_state <= A;
end if;

when B =>
random_delay_BE <= conv_std_logic_vector(BE, 3);

if beacon_period = '1' then
random_delay_pause <= '0';
else
random_delay_pause <= '1';
end if;

random_delay_en <= '1';

if random_delay_done = '1' then
next_state <= C;
else
next_state <= B;
end if;

when C =>
if (BSD / UBT) * 2 ** BO - conv_integer(counter_Backoff_period) >= 5
or ((BSD / UBT) * 2 ** BO - conv_integer(counter_Backoff_period) = 4 and conv_integer(packet_length) <= 18) then

CCA_en <= '1';

case CCA_result is
when "00" => next_state <= C; -- no results yet
when "01" => next_state <= D; -- channel busy
when "10" => next_state <= E; -- channel free
when others => null;
end case;

else
CCA_en <= '0';
next_state <= C;
end if;

when D =>
CW := 2;
NB := NB + 1;
BE := BE + 1;

if BE > aMaxBE then
BE := aMaxBE;
else null;
end if;

if NB > macMaxCSMABackoffs then
next_state <= Failure;
else
next_state <= B;
end if;

when E =>
CW := CW - 1;

if CW = 0 then
next_state <= Success;
else
next_state <= C;
end if;

when Failure =>
CSMA_CA_result <= "01";
next_state <= Failure;

when Success =>
CSMA_CA_result <= "10";
next_state <= Success;

when others => null;

end case;
end process;
end behavior;


Here is the result of synthesis in Xilinx ISE:


Synthesizing Unit <csma_ca_controller>.
Related source file is "C:/ZigBeeProcessorIntegration/CSMA_CA_controller_test4.vhd".
Using one-hot encoding for signal <present_state>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <present_state> of Case statement line 75 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'init' attribute on signal <present_state> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
WARNING:Xst:737 - Found 7-bit latch for signal <next_state>.
Found 1-bit 4-to-1 multiplexer for signal <random_delay_pause>.
Found 1-bit 4-to-1 multiplexer for signal <CCA_en>.
Found 21-bit adder for signal <$n0006> created at line 104.
Found 21-bit comparator greatequal for signal <$n0011> created at line 104.
Found 8-bit comparator lessequal for signal <$n0013> created at line 104.
Found 4-bit comparator greater for signal <$n0018> created at line 126.
Found 7-bit register for signal <present_state>.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 3 Comparator(s).
inferred 2 Multiplexer(s).
Unit <csma_ca_controller> synthesized.


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
_n0028(_n00281:O) | NONE(*)(next_state_5) | 7 |
CLK | BUFGP | 14 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.



I have another FSM which pass the synthesis perfectly!!! and I just can't find the differences between these two next_state !!! here is the code for this correct one:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity depackager_controller is
port(
CLK : in std_logic;
reset : in std_logic;
rts : in std_logic;
comparator_output : in std_logic;
request : in std_logic;
exam_microprocessor : in std_logic;
counter2_output : in std_logic_vector(7 downto 0);
counter1_rst : out std_logic;
counter1_en : out std_logic;
r_w : out std_logic;
crc_reg_en : out std_logic;
rtr : out std_logic;
comparator_en : out std_logic;
counter1_trigg : out std_logic;
counter2_en : out std_logic;
counter2_trigg : out std_logic;
ack : out std_logic;
crc_reg_initialize : out std_logic;
crc_reg_trigg : out std_logic;
counter2_initialize : out std_logic;
address_loc : out std_logic_vector(7 downto 0);
multiplexer_select_data : out std_logic_vector(1 downto 0);
multiplexer_select_address : out std_logic_vector(1 downto 0));
end depackager_controller;

architecture behavior of depackager_controller is
type state_type is (A, B, C, C1, C2, D, D1, E, E1, E2, F, G, G1, H, H1, I, J);
signal present_state, next_state : state_type;
begin
process (CLK)
begin
if CLK'event and CLK = '1' then
if reset = '1' then
present_state <= A;
else
present_state <= next_state;
end if;
else null;
end if;
end process;

process (rts, comparator_output, counter2_output, request, present_state, exam_microprocessor)
begin
-- The default value for all the output signals
r_w <= '1';
counter1_rst <= '0';
counter1_en <= '0';
crc_reg_en <= '0';
comparator_en <= '0';
rtr <= '0';
counter1_trigg <= '0';
counter2_en <= '0';
counter2_trigg <= '0';
counter2_initialize <= '0';
crc_reg_trigg <= '0';
crc_reg_initialize <= '0';
ack <= '0';
multiplexer_select_data <= "00";
multiplexer_select_address <= "00";
address_loc <= "00000000";


case present_state is
when A => counter1_rst <= '1'; counter1_en <= '1'; crc_reg_initialize <= '1'; next_state <= B;

when B => counter1_en <= '1'; comparator_en <= '1';
if rts = '1' then
next_state <= C;
else
next_state <= B;
end if ;

when C => rtr <= '1'; comparator_en <= '1'; counter1_en <= '1'; counter1_trigg <= '1'; next_state <= C1;

when C1 => comparator_en <= '1'; counter1_en <= '1'; next_state <= C2;

when C2 => comparator_en <= '1'; counter1_en <= '1';
if comparator_output = '0' then
next_state <= B;
else
next_state <= D;
end if;

when D => multiplexer_select_address <= "01"; address_loc <= "10000000"; next_state <=D1;

when D1 => multiplexer_select_address <= "01"; counter2_en <= '1'; counter2_initialize <= '1'; r_w <= '0';
if rts = '1' then
next_state <= E;
else
next_state <= D1;
end if;

when E => rtr <= '1'; counter2_en <= '1'; counter2_trigg <= '1'; crc_reg_en <= '1'; next_state <= E1;

when E1 => counter2_en <= '1'; crc_reg_en <= '1'; next_state <= E2;

when E2 => counter2_en <= '1'; r_w <= '0'; crc_reg_en <= '1'; crc_reg_trigg <= '1'; next_state <= F;

when F => crc_reg_en<= '1'; counter2_en <= '1';
if counter2_output = "00000000" then
next_state <= G;
else if rts= '1' then
next_state <= E;
else
next_state <= F;
end if ;
end if;

when G => multiplexer_select_data <= "10"; address_loc <= "10000001"; multiplexer_select_address <= "01"; next_state <= G1;

when G1 => r_w <= '0'; multiplexer_select_data <= "10"; address_loc <= "10000001"; multiplexer_select_address <= "01"; next_state <= H;

when H => multiplexer_select_data <= "01"; address_loc <= "10000010"; multiplexer_select_address <= "01"; next_state <= H1;

when H1 => r_w <= '0'; multiplexer_select_data <= "01"; address_loc <= "10000010"; multiplexer_select_address <= "01"; next_state <= I;

when I => multiplexer_select_address <= "10";
if request = '1' then
next_state <= J;
else
next_state <= I;
end if;

when J => ack <= '1'; multiplexer_select_address <= "10";
if exam_microprocessor = '0' then
next_state <= A;
else
next_state <= J;
end if;
end case;
end process;
end behavior;


Any one can tell me where is the bug for that next_state???? thank you very much!!!!!

 

[robelsner]

You might consider assigning a default value for next_state before your case statement, since a latch will be inferred if next_state is not guaranteed a value. Or put next_state <= ERROR in your when others.