Frequency Divisor 1

[pongi]

I need a code to implemet a frequency divisor. I use an Altera Apex20KE for my thesis. I've just done so with schematic blocks and library elements or with some file in VHDL. Now I would do the same thing with an only one file VHDL. I would use a variable wich define how many DFF in cascade to use in the divisor (every DFF with negative feedback = frequency/2). I hope someone can understand my bad english and help me. Thanx to everyone.
Pongi.

 

[ahedin]

--this uses a generic to determine the number of stages
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clockdiv2 is
generic (DIV : positive := 10); --number of stages > 0

port (Clear : in std_logic;
CLK : in std_logic;
Dout : out std_logic);

end clockdiv2;


architecture rtl of clockdiv2 is

signal counter : std_logic_vector(DIV downto 1);

begin

--binary counter used as clock divider
main : process(Clear,CLK)
begin
if Clear = '1' then
counter <= (others => '0');
elsif rising_edge(CLK) then
counter <= counter + 1;
end if;
end process;

Dout <= counter(DIV);

end rtl;

 

[pongi]

Thanx a lot, tomorrow I'll test it.