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Frame Slips on Tie Line

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billgray

Technical User
Sep 4, 2002
43
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Tie line between 2 Option 11C's, TMDI cards at both ends. I'm getting incrementing SLIPD errors at both ends.
Both Option 11's are clocking off of the local carrier's PRI. The LD 73 DDB and LD 60 "SSCK 0" both confirm tracking to the primary clock source. There are no slips on the local PRI's at either end. The tie line loops don't have clock boards installed so at this time I can't try clocking one PBX off of the other.
The wiring has been re-punched, the carrier has tested the tie line and "of course" it tested clean. Any suggestions?
 
without a clock card on that pri, she's going to slip.. one system clocks off of ld carrier all ties to that pbx clock from that switch.. i've done 500 switches without problems following those guidelines.. because clocking is so critical in tdm it has to all be in sync

john poole
bellsouth business
columbia,sc
 
Post your DCH's for both ends
I asume one end is user and the other NET and the ifc are the same.

do you have CSU's?
bypass the CSU's for the TIE for a test


It's only dialtone-VZ
 
Yep, one side is user the other side is net, IFC SL1...I've done a hundred of these, that's kind of a no-brainer at this point. Here you go. Johnpoole I'll see if I can't implement a clock board on the tie line TMDI's.
DCH's:

ADAN DCH 13
CTYP TMDI
CARD 03
PORT 1
DES TIE_TO_(deleted)
USR PRI
DCHL 3
OTBF 32
PARM RS232 DTE
DRAT 64KC
CLOK EXT
NASA NO
IFC SL1
SIDE NET
SEMT 1
CNEG 1
RLS ID 3
RCAP ND2 MSDL TAT
MBGA NO
OVLR NO
OVLS NO
T200 3
T203 10
N200 3
N201 260
K 7

ADAN DCH 11
CTYP TMDI
CARD 02
PORT 1
DES tie_to_WPB
USR PRI
DCHL 2
OTBF 32
PARM RS232 DTE
DRAT 64KC
CLOK EXT
NASA NO
IFC SL1
SIDE USR
CNEG 1
RLS ID 3
RCAP ND2 MSDL TAT
MBGA NO
OVLR NO
OVLS NO
T200 3
T203 10
N200 3
N201 260
K 7
 
check clocking on CSUs - one end need to clock from network and the other end from pbx
 
Unless something has changed you cannot add another clock daughterboard in the same cabinet to the Tie if you already have one installed on your PSTN.

Unless your saying you have a clock daughterboard at one end but nothing on the other side then I could see it slipping

I would change my RLS to 25 for 3.0 also


It's only dialtone-VZ
 
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