hello all. i have a hierarchichal vhdl design which one port is of the "inout std_logic_vector" type. This port connects to two internal components; one as an input and the other as an output. during simulation, i cannot force a value on this port(i am using the "force" command). for some reason the signal is staying undefined. any suggestions? thanks for any help.
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forcing top level signal in modelsim xe
- Thread starter agunos
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