For loop synthesis errors

[ribs15183]

I'm attempting to synthesize some VHDL that has many nested for loops whose bounds must change so I'm using integer variables as the bounds. The error I'm getting is:

ERROR:Xst:1549 - Range bound must be a constant.

ex: for i in 15 downto ground loop
for k in 0 to fin loop <<error here>>
...
end loop;
if(something) then fin := fin + 1;
end if;
end loop;

> Where fin is a variable integer and ground is a constant.

Is there any way to avoid this without covering every case with the use of constants?

 

[HosseinMoradi]

Dear guy,
If you only want ot simulate this code you won't have any problem but for synthesising you should know that you can't use a variable for right bound of range in a for loop
you can only use canstants as bound in a for loop.

Regards,

Hossein Moradi

 

[HosseinMoradi]

Dear guy,
If you only want ot simulate this code you won't have any problem but for synthesising you should know that you can't use a variable for right bound of range in a for loop
you can only use canstants as bound in a for loop.
soyou can use acse statement and use all the values that your variable can take(EXP: 0 to 15)and for these number of choices you should repeat the code with a constant that it's boundry is that choice
EXP case fin
when 1 => for i in 15 downto ground loop
for k in 0 to 1 loop
...
end loop;
-- if(something) then fin := fin + 1;
-- end if;
end loop;
when 2 => for i in 15 downto ground loop
for k in 0 to 2 loop
...
end loop;
-- if(something) then fin := fin + 1;
-- end if;
end loop;
when others,,,
and sth like this may avoid any synthesis error!!!!.
Regards,

Hossein Moradi