FIFO

[rosluc]

Hi to everyone!

I am a beginner with VHDL, so I'm sorry if I say something extremely stupid!
I have implement a fifo code, so before starting coding I would like to know if there is any reference that you know that I can read to help me!
Of course any help is more than welcome, thank you!

 

[jeandelfrigo]

Hello Rosluc,

Let me start by saying that you don't give a lot of information on what you want.

Fifo's are very comonly used components and they exist in many flavours.

A majo distinction is synchronous and asynchronous fifos. Mainly in my work I use asynchronous ones 99% of the time.
A synchronous fifo is a fifo where output and input run on the same clock. The asynchronous one has a different clock for in an output.
So fifos are mostly used for transfering data from one clock domain to the other. For example from a DDR controller to a processing component.

Further fifos can have different features. Basic fifo has a write dataport a write clock and a write enable and a read clock, a read enable and a read dataport. Also most of the time they have status flags full and empty. Full is commonly on the write side and empty on the read side. Often you will find also almost full and almost empty flags.
You can imagine that if you start a burst read of 256 bytes when your fifo only has 5 bytes of space left will give you a problem. So it is useful in most application to have a full indication well in time before the fifo actually goes full. The same reasoning can be done for empty.
Really handy is when you have counters that give you the exact amount of space available in the fifo. A writecount that tells you how many writes yo can still perform and a readcount that tells you how much still needs to be read from the fifo.

I hope the info above makes it clear that I cannot just give you a piece of code that fits your needs.

Fifos are basically nothing more than embedded memory with control logic around. The memory is typically a RAM block in dual port mode. The control logic is logic that generate the read and write addresses for the RAM, and generates the status information.
In most modern FPGAs you have lots of block ram, but you can also build a fifos from distributed memory or flip flops in the logic elements. Also in modern FPGAs the LUTs can be used as small memories.

For example in DDR controllers it is very common to resync the data fro DQS to clock domain using tiny fifos made from a lot. Xilinx even uses the same prnciple for a small fifo in their micro uart.

The tricky part is for asynchronous fifos because you allways need topass on information from the write to the read clock domain. You want this info to get passed with minimum delay but with good resync.

This brings me to my final part of information. As fifos are a basic building block in most FPGA designs, most vendors consider it to be a "primitive". This means that for example Xilinx and Altera development tools allow you to easily build a fifousing their coregen or megawizard tools. You can even select between blockram or distributed memory. You can also select status flags, content counters, etc.

Basically this means that its a bit silly to spend time writing and testing a fifo unless you want somthing really specific or if your FPGA resources are so limited that you do no want to spend more real-estate than absolutely required.

So my advise is check the documentation of the tools and their add-ons, and play around with it. This is often the fastest and least difficult way.

In my opinion writing your own fifo yourself today is good for academic reasons, as a hobby. Unless you really want something very specific.
There is a very good reason why manufacturers provide these "cores" for free with their tools and also why for example xilinx implements hard coded fifos next to the blockrams in their virtex devices. Well they did so in virtex 4 and in virtex 5 they even made them work .

I hope this helped.

Regards,

Jeandelfrigo

 

[rosluc]

Hi Jean!

Thank you for your kind answer!

At this time anyway I menaged to implement my Sinchronous fifo. The idea was both to use it for real and to use it to learn the vhdl, as I was compelteley new to it.
Anyway I did not find any premade fifo in the xilinx documentation and software. Maybe I'll have a closer look just in case .

Thank you again, and at the next doubt!