'EVENT ERROR IN IF STATEMENT

[mat615]

I'm using Quartus to compile a DFLIPFLOP that i had created originally for Modelsim Altera, on the Modelsim it compiles great with no error on Quartus II i get the following error:

Error: VHDL Case Statement or If Statement error at DFLIPFLOP.vhd(22): can't synthesize condition that contains an isolated 'EVENT predefined attribute

below is the snippet of the code, Quartus seems not to like,

begin
process(D, CK)
variable LastEventOnD, LastEventonCK: TIME;
begin
if (D'event) then
assert (NOW = 0 ns) or (NOW - LastEventOnCK) >= HOLD_TIME
report "Hold time to short"
severity FAILURE;
LastEventOnD := NOW;
end if;
if ( rising_edge(CK) ) then
assert (NOW = 0 ns) or (NOW - LastEventonD) >= SETUP_TIME
report "SETUP time to short"
severity FAILURE;
LastEventOnCK := NOW;
end if;
if rising_edge(CK) then
Q <= D;
NOTQ <= not D;
end if;
end process;

it I were to rem the first IF statement if compiles just fine and i get the same results in my waveforms as the ones in Modelsim. Yet, i want to know why do i get this error, please if someone knows can they help me.

 

[mat615]

I'm sorry forgot to mention where might line 22 be....

begin
process(D, CK)
variable LastEventOnD, LastEventonCK: TIME;
begin
if (D'event) then <--- Line 22
assert (NOW = 0 ns) or (NOW - LastEventOnCK) >= HOLD_TIME
report "Hold time to short"
severity FAILURE;
LastEventOnD := NOW;
end if;
if ( rising_edge(CK) ) then
assert (NOW = 0 ns) or (NOW - LastEventonD) >= SETUP_TIME
report "SETUP time to short"
severity FAILURE;
LastEventOnCK := NOW;
end if;
if rising_edge(CK) then
Q <= D;
NOTQ <= not D;
end if;
end process;

 

[VhdlForLife]

Most synthesis tools have stricter rules than simulation tools since they have to produce hardware that works. One of the most common rule of thumbs you should keep in mind is that synthesizers usually don't like more than one type of edge triggered event in a process. Processes that are synchronous can only have one edge triggered signal (usually a clock) and a level triggered signal (usually an asynchronous reset) at the top level. All other signals will have to be combinational.