ERROR Definition

[Oppenheimer]

Hi All,
I'm one of the new members of this discussion platform. And I'm also beginner about the VHDL. I have XLINX CoolRunner-II CPLD bord and I'm trying to learn VHDL. Nowadays, I design a simple counter code to count from 0 to 9 on the seven segment display. But there is an error which I could not understand. You can see my code.In the code UpBtn and DownBtn inputs are stimuluses to increase and decrease the number.

ERROR:HDLParsers:164 - "C:/CPLD_Designs/0-9_UpDown_Counter/NewCounter/Counter/Counter.vhd" Line 73. parse error, unexpected PROCESS, expecting IF

If you comment on the error and write it I'll be grateful to you.
Thanks,
Oppenheimer.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Counter is
Port ( UpBtn : in STD_LOGIC;
DownBtn : in STD_LOGIC;
Data : out STD_LOGIC_VECTOR (6 downto 0):= "0111111" );
end Counter;

architecture Behavioral of Counter is
shared variable bcd: integer:= 0 ;
begin

process (UpBtn,DownBtn)
variable off: STD_LOGIC_VECTOR (6 downto 0):= "0000000" ;
variable zero: STD_LOGIC_VECTOR (6 downto 0):= "0111111" ;
begin
if rising_edge(UpBtn) then
if bcd= 9 then
bcd:= 0;
else
bcd:=bcd+1;
end if;
else if rising_edge(DownBtn) then
if bcd = 0 then
Data<= off;
Data<= zero after 500 ms;
else
bcd:=bcd-1;
end if;
end if;

case bcd is
when 0 => Data<= "0111111";
when 1 => Data<= "0000110";
when 2 => Data<= "1011011";
when 3 => Data<= "1001111";
when 4 => Data<= "1100110";
when 5 => Data<= "1101101";
when 6 => Data<= "1111101";
when 7 => Data<= "0000111";
when 8 => Data<= "0111111";
when 9 => Data<= "1101111";
when others => Data <= "1000000";
end case;

end process; (LINE:73)

end Behavioral;

 

[blacktom]

Hello Oppenheimer,

I think the following piece of code is causing the trouble.

Data<= zero after 500 ms;

You can't use a delay this way in RTL.
The compiler doesn't understand this.
You have to define your delay in another way.

You can use this in Testbenches to test your design by
raising signals on a precise moment.

Good luck

 

[Oppenheimer]

Thanks blacktom,

I have revised the code and thought about your suggestion. But now I have another problem which is about signal "bcd".
On the other hand, when I tried to get out case statemnet from the process( to put it another process which has a sensitivity list as "bcd") it gives another error about the case statement. I could not understand.

Waiting your comments.
Thanks,
Oppenheimer.

My new error is:

ERROR:Xst:827 - "C:/CPLD_Designs/0-9_UpDown_Counter/NewCounter/Counter/Counter.vhd" line 41: Signal bcd cannot be synthesized, bad synchronous description.



entity Counter is
Port ( UpBtn : in STD_LOGIC;
DownBtn : in STD_LOGIC;
Data : out STD_LOGIC_VECTOR (6 downto 0):= "0111111" );
end Counter;

architecture Behavioral of Counter is
signal bcd: STD_LOGIC_VECTOR (3 downto 0) := "0000" ;

begin

process (UpBtn,DownBtn)
variable off: STD_LOGIC_VECTOR (6 downto 0):= "0000000" ;
variable zero: STD_LOGIC_VECTOR (6 downto 0):=
"0111111" ;
begin
if rising_edge(UpBtn) then
if bcd = "1001" then
bcd<= "0000" ;
else
bcd<=bcd + 1;
end if;
else if rising_edge(DownBtn) then
if bcd = "0000" then
Data<= off;
Data<= zero after 500 ms;
else
bcd<=bcd - 1;
end if;
end if;
end if;

case bcd is
when "0000" => Data<= "0111111";
when "0001" => Data<= "0000110";
when "0010" => Data<= "1011011";
when "0011" => Data<= "1001111";
when "0100" => Data<= "1100110";
when "0101" => Data<= "1101101";
when "0110" => Data<= "1111101";
when "0111" => Data<= "0000111";
when "1000" => Data<= "0111111";
when "1001" => Data<= "1101111";
when others => Data <= "1000000";
end case;

end process;


end Behavioral;

 

[dsimon19]

Hi Oppenheimer,

I am not sure but I guess using 2 rising edge function in a single process to assign a unique signal bcd will not be liked by any synthetizer. Think about it you want to register a signal bcd and you want it to be registred with 2 different clocks I can't see how it can work.
I would suggest to separate process or think about using a front edge detection signal instead of the primitive rising edge.
Let us know how it goes.

Regards.

 

[Oppenheimer]

Thanks for your valuable suggestions,
I have revized the code and collected all signals under the name of Cclk.
signal Cclk: std_logic ;
Command line is: Cclk<= UpBtn or DownBtn or Rst or clk ;
process (Cclk,bcd)
..
..
end process;

So that, I passed the error. Now my program works very well. Also I have simulated the code and the result was excellent. But now I have another problem which I need some help. I have generated programming file and (I use WebPack-ISE9.1i) loaded it to the my CPLD board. program does not work on the board. It just displays zero on the seven segmet. I have controlled all necessary pis of the cpld by my oscilloscope. everything is ok. What do you think about this. Have you ever met as this problem before?
And by the way, one more thing about VHDL. as far as I know, all vhdl commands can not be executed by the compiler. Do you know something about this topic? Is there any document that you recomend to me?
Thanks,
Oppenheimer.

 

[dsimon19]

Hi Oppenheimer,

Happy it works!!
I still do not understand why you put clk and rst on the same net. When using clocked process you usually have in the sensitivity list clock + reset. Reset is used to initialized signals, you can't use ':='operator to do that in real life (especially on entity port!!). I am not sure your counter is getting out of reset correctly!!

Are you sure your code has been synthesized correctly?
It can happen that ISE does not point error that will make the synthesized process stop with failure but does not synthesized part of the logic.
In that case it gives a warning only. Have a look in your synthesis report to check if every went fine.

There is no code compiler for VHDL but a tool that take the source code and transform it to netlist (your circuit). VHDL is not a software langage it is an Hardware Description Langage. You can find lots of documentation on the web.

Regards

Damien

 

[Oppenheimer]

Hi dsimon19,

Thank you verymuch, because of your suggestions and ideas. I have realised what you wanted to imply by 'warining message'. Yes there are lots of warning without any error.(Ahhahh!)But, what can be the reason I "could not" find the reason! It drives me crazy(Puuaahh!!)I have tried so many things. And the last version of my vhdl code is below. Please clarify the situation. I'm at the starting point of the vhdl road. There are to many details. How can I approach to the topic with a conscious and cool way? I have downloaded somany documents, but %90 of them are rubish.

Regards,
Oppenheimer

---------------------------------------------------------------------
WARNING:Xst:2170 - Unit Sayici : the following signal(s) form a combinatorial loop: clock_cmp_eq0000, value<0>.
WARNING:Xst:2170 - Unit Sayici : the following signal(s) form a combinatorial loop: value<0>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<1> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<1>, Result, Data<1>, Sayici/value<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<2> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<2>, Result, Sayici/value<2>, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<3> : the following signal(s) form a combinatorial loop: Data<1>, Sayici/value<3>, Result, Sayici/value_addsub0000<3>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<4> : the following signal(s) form a combinatorial loop: Sayici/value<4>, Result, Sayici/value_addsub0000<4>, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<5> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<5>, Sayici/value<5>, Result, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<6> : the following signal(s) form a combinatorial loop: Data<1>, Sayici/value<6>, Sayici/value_addsub0000<6>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<7> : the following signal(s) form a combinatorial loop: Data<1>, Sayici/value<7>, Result, Sayici/value_addsub0000<7>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<8> : the following signal(s) form a combinatorial loop: Result, Data<1>, Sayici/value_addsub0000<8>, Sayici/value<8>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<9> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<9>, Sayici/value<9>, Result, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<10> : the following signal(s) form a combinatorial loop: Result, Sayici/value_addsub0000<10>, Sayici/value<10>, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<11> : the following signal(s) form a combinatorial loop: Sayici/value<11>, Sayici/value_addsub0000<11>, Data<1>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<12> : the following signal(s) form a combinatorial loop: Data<1>, Result, Sayici/value_addsub0000<12>, Sayici/value<12>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<13> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<13>, Data<1>, Result, Sayici/value<13>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<14> : the following signal(s) form a combinatorial loop: Sayici/value<14>, Sayici/value_addsub0000<14>, Data<1>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<15> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<15>, Data<1>, Result, Sayici/value<15>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<16> : the following signal(s) form a combinatorial loop: Sayici/value<16>, Data<1>, Sayici/value_addsub0000<16>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<17> : the following signal(s) form a combinatorial loop: Data<1>, Result, Sayici/value<17>, Sayici/value_addsub0000<17>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<18> : the following signal(s) form a combinatorial loop: Data<1>, Sayici/value<18>, Sayici/value_addsub0000<18>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<19> : the following signal(s) form a combinatorial loop: Sayici/value<19>, Result, Sayici/value_addsub0000<19>, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<20> : the following signal(s) form a combinatorial loop: Result, Sayici/value<20>, Sayici/value_addsub0000<20>, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<21> : the following signal(s) form a combinatorial loop: Sayici/value<21>, Result, Data<1>, Sayici/value_addsub0000<21>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<22> : the following signal(s) form a combinatorial loop: Result, Sayici/value_addsub0000<22>, Sayici/value<22>, Data<1>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<23> : the following signal(s) form a combinatorial loop: Result, Sayici/value<23>, Data<1>, Sayici/value_addsub0000<23>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<24> : the following signal(s) form a combinatorial loop: Result, Data<1>, Sayici/value<24>, Sayici/value_addsub0000<24>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<25> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<25>, Data<1>, Result, Sayici/value<25>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<26> : the following signal(s) form a combinatorial loop: Sayici/value_addsub0000<26>, Data<1>, Sayici/value<26>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<27> : the following signal(s) form a combinatorial loop: Sayici/value<27>, Sayici/value_addsub0000<27>, Data<1>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<28> : the following signal(s) form a combinatorial loop: Sayici/value<28>, Data<1>, Sayici/value_addsub0000<28>, Result.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<29> : the following signal(s) form a combinatorial loop: Result, Sayici/value<29>, Data<1>, Sayici/value_addsub0000<29>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<30> : the following signal(s) form a combinatorial loop: Data<1>, Sayici/value<30>, Result, Sayici/value_addsub0000<30>.
WARNING:Xst:2170 - Unit Madd_value_addsub0000_Mxor_Result<31> : the following signal(s) form a combinatorial loop: Data<1>, Sayici/value_addsub0000<31>, Result, Sayici/value<31>.
---------------------------------------------------------------------
VHDL Code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Library UNISIM;
--use UNISIM.vcomponents.all;

entity Sayici is
Port ( clk : in STD_LOGIC; --system clk
rst : in STD_LOGIC; --main reset
upbtn : in STD_LOGIC; --up buton
downbtn : in STD_LOGIC; --down buton
cs : out STD_LOGIC; --segment selector
data : out STD_LOGIC_VECTOR (6 downto 0)) ; --output data bus
end Sayici;

architecture Behavioral of Sayici is
signal Cclk,enb,scanclk,clock: STD_LOGIC:= '0';
signal value: STD_LOGIC_VECTOR (31 downto 0):= "00000000000000000000000000000000";
signal bcd,bcd1,bcd2: STD_LOGIC_VECTOR (3 downto 0) := "0000" ;

begin
process(clk)
begin
if rising_edge(clk) then
Cclk<= upbtn or downbtn or rst;
end if;
end process;

enb<= not Cclk and (upbtn or downbtn or rst);

process(clk)

begin
if rising_edge(clk) then
if enb= '1' then
if rst= '1' then
bcd1<= "0000";
bcd2<= "0000";
end if;

if UpBtn= '1' then
if bcd1= "1001" then
if bcd2= "1001" then
bcd1<= "0000";
bcd2<= "0000";
else
bcd2<= bcd2 + 1;
bcd1<= "0000";
end if;
else
bcd1<=bcd1 + 1;
end if;
end if;

if DownBtn= '1' then
if bcd1= "0000" then
if bcd2= "0000" then
bcd1<= "1001";
bcd2<= "1001";
else
bcd1<= "1001";
bcd2<= bcd2 - 1;
end if;
else
bcd1<=bcd1 - 1;
end if;
end if;
end if;
end if;

end process;

-- clk_div16_inst1 : clk_div16
-- port map (
-- clkdv => div1, -- Divided clock output
-- clkin => clk ); -- Clock input
--
-- clk_div16_inst2 : clk_div16
-- port map (
-- clkdv => div2, -- Divided clock output
-- clkin => div1 ); -- Clock input
--
-- clk_div16_inst3 : clk_div16
-- port map (
-- clkdv => div3, -- Divided clock output
-- clkin => div2 ); -- Clock input
--
-- clk_div16_inst4 : clk_div16
-- port map (
-- clkdv => div4, -- Divided clock output
-- clkin => div3 ); -- Clock input
--
process(clk)
begin
value<= value + 1;
if value= 500_000 then
clock<= not clock;
value<= "00000000000000000000000000000000";
else
clock<= clock;
end if;
scanclk<= clock;
cs<= scanclk;
end process;

process(scanclk)
begin
if scanclk= '0' then
bcd<= bcd1;
else
bcd<= bcd2;
end if;

case bcd2 is
when "0000" => Data<= "0111111";
when "0001" => Data<= "0000110";
when "0010" => Data<= "1011011";
when "0011" => Data<= "1001111";
when "0100" => Data<= "1100110";
when "0101" => Data<= "1101101";
when "0110" => Data<= "1111101";
when "0111" => Data<= "0000111";
when "1000" => Data<= "1111111";
when "1001" => Data<= "1101111";
when others => Data <= "1000000";
end case;
end process;

end Behavioral;

 

[dsimon19]

Hi Oppenheimer,

I am sorry I dont have enought time to correct your code.
I think you should start understanding what VHDL stands for. It is used to define an electronic circuit. So you need to have minimal basics in electronics.
VHDL has nothing to do with any computing langage, the purpose is not the same.
VHDL is used to define the hardware that is going to be used by the C language (for example) to do the job.
Many manuals are downloadable from the web, unfortunatly mine are in french so it won't help.

Basically to code clean vhdl (the one that will be synthesized like you want) you need to know if your logic is sequential or combinatory, in first case you'll be using process with clock an reset in sensitivity list like that:

Sequential: process (clock, reset)
begin
if reset = '1' then
your_signal <= '0';
elsif (clock'event and clock = '1') then
< your function >
end if;
end process;

In second case (combinatory) you are not supposed to use process.

Of course there is many way to code VHDL and you can use for instance process with many signals in sensitivity list but it is not clean. Using variables is not clean either.

Think about clocking and reset first then you can start coding your function.

I am sorry but I would need some more time to explain, but I am sure that if you spend time on manual after you have understood the concept of VHDL tool you will progress quickly. If you keep using the langage like any other programming langage you will not succeed. That is just my advice.

Good luck.

 

[Oppenheimer]

Thank you very much dsimon19 for your suggestions and interest. I'll consider your opinions and try to work carefully.
Take Care,

Oppenheimer

 

[blacktom]

Hello Oppenheimer,

I examined your last code.

The variable value is not clocked, clk is in the
sensitivity list of the process but you forgot to
include the rising_edge(clk) statement.

The same goes for the data outputs.

Also signal bcd is not driving anything and can
be skipped.

Good luck

Blacktom