Division in VHDL with std_logic_vector

[danell]

I need to implement a chaotic function in a design with VHDL. I use std_logic_vector signals and I need to implement 4 divisions. However, i recieve an error message saying: "Line 40. / can not have such operands in this context."

I use:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



Can you please help me?

 

[danell]

This is the code i used:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity imp is
Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0);
in2 : in STD_LOGIC_VECTOR (7 downto 0);
ies : in STD_LOGIC_VECTOR (7 downto 0));
end imp;

architecture Behavioral of imp is

begin

ies <=in1/in2;

end Behavioral;

 

[PaulieQ]

Servus,

First: port ies should be output and not input (ca doar de aia l-ai numit ies de la iesire ).

Second: you can't not divide a vector to another vector.

Best regards,
Paulie