declaration & assignment

[Guest_imported]

Okay, I'm new at this, and it might seem like a simple thing, but I cannot figure it out. When I do "check syntax" it gives me errors but it only says
" Error L23/C0 : #0 Error: C:/fndtn/active/projects/alu/alu.vhd line 23 Syntax error. (VSS-1081) "

It doesn't really tell me what's wrong

here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ALU is
port (
A: in STD_LOGIC_VECTOR (3 DOWNTO 0);
B: in STD_LOGIC_VECTOR (3 DOWNTO 0);
OP: in STD_LOGIC_VECTOR (1 DOWNTO 0);
CLK: in STD_LOGIC;
C: out STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end ALU;

architecture ALU_arch of ALU is
begin
process (CLK)
begin

A <= &quot;0101&quot;
B <= &quot;0010&quot;; -- *error here*

if (CLK = '1') then
case op(1 downto 0) is
when &quot;00&quot; => C <= A + B;
when &quot;01&quot; => C <= A + (not B);
when &quot;10&quot; => C <= A and B;
when &quot;11&quot; => C <= not A;
when others => C <= A;
end case;
end if;
end process;
end ALU_arch;

If I don't put the semicolon, it gives me 2 errors for that line and the next line.
If I put semicolons in the statement before that line, it also gives 2 errors.
I don't know what's wrong...someone please help!!!
Thanks!

 

[Guest_imported]

never mind, figured it out!

 

[sunil287]

Hi ,
You are trying to drive input signals A and B which is not allowed.

 

[vhdlverilog]

u missed out a semocolon( after the assignment to signal a

hope u might have got it by now

 

[sgarg]

In if loop u r using only one condition that clk='1' well it is not good as some synthesis tool donot take functionality implied from process senstivity list. so better practice is to use like:

if(clk'event and clk='1') then

--code

end if

Such errors raise synthesis problems.

 

[Guest_imported]

-- From Mehdi Ghavidel
--- My Email : ghavidel_11356@yahoo.com -- Please contact me for more information or other problems.
-- Corrected VHDL Code for your projects Written below.
--lvyndr (Visitor) Jul 18, 2001
--Okay, I'm new at this, and it might seem like a simple thing, but I cannot figure it out. When I do &quot;check syntax&quot; it gives me errors but it only says
--&quot; Error L23/C0 : #0 Error: C:/fndtn/active/projects/alu/alu.vhd line 23 Syntax error. (VSS-1081) &quot;

--It doesn't really tell me what's wrong

--here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ALU is
port (
A: inout STD_LOGIC_VECTOR (3 DOWNTO 0);-- I change IN to INOUT .
B: inout STD_LOGIC_VECTOR (3 DOWNTO 0);-- I change IN to INOUT.
OP: in STD_LOGIC_VECTOR (1 DOWNTO 0);
CLK: in STD_LOGIC;
C: out STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end ALU;

architecture ALU_arch of ALU is
begin
process (CLK,A,B,OP) -- This signals A,B,OP shulde be added into procces sensivity list.
begin

A <= &quot;0101&quot; ; -- * PLease put this semicolon. ok?* you can't write into A & B, because you set then for inpot . i change them statuse into INOUT.
B <= &quot;0010&quot;; -- *error here*

if (CLK = '1') then
case op(1 downto 0) is
when &quot;00&quot; => C <= A + B;
when &quot;01&quot; => C <= A + (not B);
when &quot;10&quot; => C <= A and B;
when &quot;11&quot; => C <= not A;
when others => C <= A;
end case;
end if;
end process;
end ALU_arch;
--*** Your code check Successful ***
-- Your Friend Mehdi Ghavidel From IRAN(Tehran) ---

--If I don't put the semicolon, it gives me 2 errors for that line and the next line.
--If I put semicolons in the statement before that line, it also gives 2 errors.
--I don't know what's wrong...someone please help!!!
--Thanks!