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creating a make file

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CaptRage61

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Feb 17, 2005
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Does anyone know how to create a make file? For example, I have 3 c programs: myprog1.c, myprog2.c and myprog3.c. How do I creat a make file that will compile all of these programs by 1 command and make them executable???
 
That link is to the GNU manual for Make. If your question is "How do I write a Makefile?", then you should read the manual.

If you have specific questions after reading the introductory sections of the manual, ask those. And preferably with more detail. For example, you mentioned three source files (not three programs); do you want to compile them all into one large program, or do you want to compile each source file into its own program?
 
Here is what I have for a makefile, I have the 3 files myprog1.c, myprog2.c and myprog3.c and I want to make 3 executable files called myprog1, myprog2 and myprog3. When I run this makefile I get errors. Here is what I have
Code:
all: myprog1.o myprog2.o myprog3.o
        cc -o all myprog1.o myprog2.o myprog3.o

myprog1.o: myprog1.c
        cc -c myprog1.c

myprog2.o: myprog2.c
        cc -c myprog2.c

myprog3.o: myprog3.c
        cc -c myprog3.c
~



bash-2.05$ make all
cc -o all myprog1.o myprog2.o myprog3.o
myprog2.o: In function `main':
myprog2.o(.text+0x0): multiple definition of `main'
myprog1.o(.text+0x0): first defined here
/usr/bin/ld: Warning: size of symbol `main' changed from 219 to 107 in myprog2.o
myprog3.o: In function `main':
myprog3.o(.text+0x98): multiple definition of `main'
myprog1.o(.text+0x0): first defined here
/usr/bin/ld: Warning: size of symbol `main' changed from 107 to 178 in myprog3.o
collect2: ld returned 1 exit status
make: *** [all] Error 1

Does anyone know why?
 
Code:
cc -o all myprog1.o myprog2.o myprog3.o
This line says to compile all three source files together into a single executable named "all."

The errors you get say that all your source files contain a [tt]main[/tt] function; an executable can only have one [tt]main[/tt] defined.

You probably meant for the target [tt]all[/tt] to depend on the three executables you want to create, and then have a separate rule to compile each executable.


Of course, Make usually defines implicit rules for compiling object files and for linking executables made of a single object file. Thus, you probably only need to have [tt]all[/tt] depend on your three programs and Make can figure everything else out.
 
So I would say

all: myprog1.o myprog2.o myprog3.o
cc -o all myprog1.o
cc -o all myprog2.o
cc -o all myprog3.o


Thanks
 
That'll work.

The disadvantage of your file is that if you change [tt]myprog2.c[/tt], your Makefile will cause all three programs to be rebuilt even though the other source files haven't changed.


The usual way, which I suggested above, is to have [tt]all[/tt] depend on the executables, and then have a separate rule to compile each executable:
Code:
all: myprog1 myprog2 myprog3

myprog1: myprog1.o
        cc -o myprog1 myprog1.o

myprog2: myprog2.o
        cc -o myprog2 myprog2.o

myprog3: myprog3.o
        cc -o myprog3 myprog3.o

That will rebuild only the executables whose source files have changed and leave the rest alone.


The simple way, using the implicit rules I mentioned, is:
Code:
all: myprog1 myprog2 myprog3

That'd be your whole Makefile. It also only rebuilds executables whose sources have changed. It'll only work as long as you only have exactly one source file per executable, though.
 
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