Constants and Port Maps

[CrimsonM]

Hello,

I am trying to figure out how to map a constant to a port in a component instantiation.

I have a package that contains several types, namely the following:
-------------------------------------------------
type ALPHA is array (natural range <>) of
std_logic_vector((DATAWORD/2 - 1) downto 0); -- alphabet array
constant ALPHA_LUT: ALPHA := (0 => &quot;0001&quot;, 1 => &quot;0011&quot;, 2 => &quot;0101&quot;,
3 => &quot;1001&quot;, 4 => &quot;1101&quot;, 5 => &quot;1111&quot;
-- Original 8-bit DCT coefficients
-- a=0.49, b=0.46, c=0.42, d=0.35, e=0.28, f=0.19, g=0.10
-------------------------------------------------
This creates a constant array of 6 std_logic_vectors. Now, how is it I can assign this to a port? I want to do something like below. However, this gives me an error since I am assigning a std_logic_vector to a constant I assume. I could hardwire the ports, but I do not want that. I need the package to contain constants and types so that any changes are reflected in many blocks.

This is what I have now, and it is wrong.
-------------
port map (
y0 => ALPHA_LUT(0),
-- .... more here
);
-------------

Thanks.

 

[almahtar]

I wrote up some sample code to try a few things out... it seems to work fine for me. The following code compiles just fine:


--Declare all your libraries, etc--
--SmallerItem is the item you will instantiate as a component.
--In this case I just used 3 downto 0 as its size.
entity SmallerItem is
--g_p is &quot;Global_Port&quot;
Port (g_p: std_logic_vector(3 downto 0 ));
end SmallerItem;

architecture Behavioral of SmallerItem is
begin
end Behavioral;


--Declare any additional libraries, etc--
--BiggerItem is the part in which we will instantiate
--SmallerItem as a component.

entity BiggerItem is
port (clock: in std_logic);
end BiggerItem;


architecture Behavior of BiggerItem is

----------------Your code---------------------------------
type ALPHA is array (natural range <>) of
std_logic_vector(3 downto 0); -- alphabet array

constant ALPHA_LUT: ALPHA := (0 => &quot;0001&quot;, 1 => &quot;0011&quot;,
2 => &quot;0101&quot;,3 => &quot;1001&quot;, 4 &quot;1101&quot;,
5 => &quot;1111&quot;
----------------End your code-------------------------------

component MyComponent
Port (g_p: std_logic_vector(3 downto 0 ));
end component;

begin
--Map our ports.
Comp_1: MyComponent port map ( g_p => ALPHA_LUT(0));

end Behavior;

Hope this helps you figure out what is and what isn't the problem, but quite evidently it doesn't mind mapping a constant std_logic_vector to a nonconstant std_logic_vector.

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It is an honor to recieve an honest reply. (Prov 24:26)