coding help

[sheenjrg]

guys I m using the following code to generate a 24MHZ clock from a 16Mhz clock but I do not get the desired clock. Can anyone tell me why?? (Clk_in is a 16Mhz clk)

library....
....

entity clk3x is

port
(CLK_IN, RST_DLL : in std_logic;
CLK24Mhz, LOCKED : out std_logic);
end clk3x;

architecture STRUCT of clk3x is

attribute CLKFX_MULTIPLY : string;
attribute CLKFX_DIVIDE : string;
attribute CLKFX_MULTIPLY of U2 : label is "3";
attribute CLKFX_DIVIDE of U2 : label is "2";
signal CLK, CLK_int, CLK_dcm, CLKFX_int, LCK_int, RST_int: std_logic;
signal DUMMY : std_logic := '0';

component IBUFG
port (I : in std_logic; O : out std_logic);
end component;

component BUFG
port (I : in std_logic; O : out std_logic);
end component;

component DCM is

port
(CLKFB,CLKIN,DSSEN,PSCLK,PSEN,PSINCDEC,RST : in std_logic;
CLK0,CLK90,CLK180,CLK270,CLK2X,CLK2X180,CLKDV,
CLKFX,CLKFX180,LOCKED,PSDONE : out std_logic;

STATUS : out std_logic_vector (7 downto 0));
end component;

begin




U1 : IBUFG port map (I => CLK_IN, O => CLK_int);
U2 : DCM port map (CLKIN => CLK_int,
CLKFB => CLK,
RST => RST_int,
DSSEN => DUMMY,
PSINCDEC => DUMMY,
PSEN => DUMMY,
PSCLK => DUMMY,
CLK0 => CLK_dcm,
CLKFX => CLKFX_int,
LOCKED => LCK_int
);

U3 : BUFG port map
(I => CLK_dcm, O => CLK);
RST_int <= RST_DLL;
CLK24MHZ <= CLKFX_int;
LOCKED <= LCK_int;
end architecture STRUCT;

 

[berett]

The code does not say too much ...

BTW it is impossible to simly create 24 MHz from 16 MHz. In digital way - you need some much faster clock, use a counter etc. Otherwise you need something analogue. I don't see any &quot;faster&quot; clock here so I don't see any possibility to get the 24 MHz in digital way ... and the analogue thing will not operate in the VHDL simulator ... confusing indeed.

 

[sheenjrg]

We can use a dll to multiply or divide a clock in virtex or spartan(I am not very sure about spartan) by multiples of 2 to 32 as said in the Xilinx online application notes. getting a double or four times multiple is easy but I need a 1.5 times clk. I can use a 32 Mhz but its multiple is 0.75 which is invalid in spartan.

The code is correct for a 1.5 times clk but I am not sure if I am assigning all variable correctly.

 

[naraic]

sheenjrg,

Try setting the DFS_FREQUENCY_MODE attribute to LOW.

attribute DFS_FREQUENCY_MODE : string;
attribute DFS_FREQUENCY_MODE of U2 : label is "LOW";

If this doesn't work, try set it to HIGH.

I don't know what the default is.

Ciarán Hughes

 

[naraic]

Just a thought,

The DLL input frequency range is 24 -> 326 MHz. 16 MHz falls short of this.

Try using the 32 MHz frequency, and set the divide attribute to 4 and the multiply attribute to 3.

Ciarán Hughes