Having an issue with one of our 81C clock controllers. It seems the active clock isn't seeing the inactive clock causing a DTC010. Posted below.
ssck 0 full
ENBL
CLOCK ACTIVE
GROUP 1
SIDE 0
CLOCK CONTROLLER - LOCKED TO LOOP 22
PREF - 22
SREF - 51
AUTO SWREF CLK - ENBL
NO UART
CARDID: NTRB53AA26NNTMENC87JG6
BANK 0 FIRMWARE VERSION: 019
BANK 1 FIRMWARE VERSION: 016
ACTIVE BANK: 0
FPGA VERSION: 014
CLOCK TO CLOCK CABLE: PRESENT
.ssck 1 full
ENBL
STANDBY
GROUP 2
SIDE 1
CLOCK CONTROLLER - LOCKED TO LOOP 22
PREF - 22
SREF - 51
AUTO SWREF CLK - ENBL
NO ERROR
CARDID: NTRB53AA26NNTMENC87JF8
BANK 0 FIRMWARE VERSION: 019
BANK 1 FIRMWARE VERSION: 016
ACTIVE BANK: 0
FPGA VERSION: 014
CLOCK TO CLOCK CABLE: PRESENT
My question is should I have a maintenance window when switching clocks and is the different Firmware Versions an issue?
Switch is:
Version 3621
Release 4
Issue 50 W +
ssck 0 full
ENBL
CLOCK ACTIVE
GROUP 1
SIDE 0
CLOCK CONTROLLER - LOCKED TO LOOP 22
PREF - 22
SREF - 51
AUTO SWREF CLK - ENBL
NO UART
CARDID: NTRB53AA26NNTMENC87JG6
BANK 0 FIRMWARE VERSION: 019
BANK 1 FIRMWARE VERSION: 016
ACTIVE BANK: 0
FPGA VERSION: 014
CLOCK TO CLOCK CABLE: PRESENT
.ssck 1 full
ENBL
STANDBY
GROUP 2
SIDE 1
CLOCK CONTROLLER - LOCKED TO LOOP 22
PREF - 22
SREF - 51
AUTO SWREF CLK - ENBL
NO ERROR
CARDID: NTRB53AA26NNTMENC87JF8
BANK 0 FIRMWARE VERSION: 019
BANK 1 FIRMWARE VERSION: 016
ACTIVE BANK: 0
FPGA VERSION: 014
CLOCK TO CLOCK CABLE: PRESENT
My question is should I have a maintenance window when switching clocks and is the different Firmware Versions an issue?
Switch is:
Version 3621
Release 4
Issue 50 W +