Clock Frequency

[jaredm]

Does anybody know how to define clock frequency in vhdl?

 

[RVSachin]

Clock frequency is usually set as an external constraint, i.e., external to the source code. Synthesis tools will try to meet this constraint as far as possible and better still it will run at frequencies better than the specified freq. if it is possible.

 

[CJ199]

Here is a clock frequency divider

----------------------------------------------------------------------------
--                         CLK FREQUENCY DIVIDER                          --
----------------------------------------------------------------------------
library IEEE; 
use IEEE.std_logic_1164.all; 

entity Divider is 
    port ( 
        	CLK: in STD_LOGIC; 
        	COUT: out STD_LOGIC 
   		 ); 
end Divider; 

architecture Divider of Divider is 
----------------------------------------------------------------------------
--   Output Frequency = (Altera clk 25.175 Mhz) / (2 * (TIMECONST ^ 4) )  --
--                   25.175*10^6 hz / (2 * x^4 ) = 1hz                    --
--                            x=59.56 ~ 60                                --
----------------------------------------------------------------------------
constant TIMECONST : integer := 59;  --temp at 1 or 2 for simulation purposes
signal count0, count1, count2, count3: integer range 0 to 1000 := 0; 
signal D: STD_LOGIC := '0'; 

begin 	 
     process (CLK) 
     begin 
      if (CLK'event and CLK = '1') then 
          count0 <= count0 + 1; 
          if (count0 = TIMECONST)   then 
         	 count0 <= 0; 
          	 count1 <= count1 + 1; 
          elsif (count1 = TIMECONST) then 
         	 count1 <= 0; 
         	 count2 <= count2 + 1; 
          elsif (count2 = TIMECONST) then 
         	 count2 <= 0; 
         	 count3 <= count3 + 1; 
          elsif (count3 = TIMECONST) then 
         	 count3 <= 0; 
         	 D <= not D; 
  	      end if; 
  	  end if;

      COUT <= D; 

	  end process; 
end Divider;