I am trying to design an asynchronous to synchronous design within a FPGA (Field programmable gate array) but have been unsuccessful so far. The exact problem is as follows :
There is a pseudo-random data stream coming at approximately 8 Mbps with respect to a 8MHz clock. The data can vary along-with its clock by +/-50ppm.. I have to take this data stream and synchronize it to another free running clock of exactly the same center frequency (8MHz). This clock is absolutely stable but it has no relationship whatsoever with the incoming clock i.e it is not phase locked. Can you suggest a digital based design for doing this to enable it to be implemented in an FPGA so that the output data stream is error free.
I tried using the dual-port RAM concept by using an 8 times the stable system clock to latch the data by generating relevant pulses and then writing this data into the RAM and reading it out on the system clock but there is a burst of errors after a certain time followed by correct data and then a burst and so on. The design works perfectly for a 4 bit repetitive pattern and also for a 16 bit word where the bits can be set to any value. However, for a pseudo-random sequence of 2~23 - 1 the problem persists.
I tried out various options but have not been able to resolve the problem.
The exact design I have used is as follows :
The incoming data is with respect to rising edge of the clock, This rising edge generates an enable to a counter which is running on 8 times the stable system clock. This counter generates two pulses viz one on the 2nd rising edge of the 8 times clock and the other at the 4th rising edge. The first pulse latches the data and increments the write address counter of the dual-port ram. The second pulse then is used as clcok to write this latched data into the Dual-port RAM. This second pulse is also used in conjuction with a flip flop running on the 8 times stable clock but on the negative edge to generate a reset for the counter and enabling circuit. Since the counter has been designed in VHDL the characteristic is that on reset the count and pulses are all set to zero. Thus the flip flop generating the rest also comes out of its active state on the next negative edge. No race around or permanent reset occurs at any point of time. This has been extensively checked out. The enabling circuit works again on the next positive edge and the procedure is repeated. The read from Dual port RAM starts after half the locations are filled up.
The problem that I have been able to trace out is in the writing section. In a Pseudo-random pattern the data latching into RAM is in error occassionally. I subsequently changed the position of pulses to give sufficient time to stabilize but with various combinations tried there is still error.
Can a solution be suggested to accomplish the task of asynchronous to synchronous design ?
Thanks
There is a pseudo-random data stream coming at approximately 8 Mbps with respect to a 8MHz clock. The data can vary along-with its clock by +/-50ppm.. I have to take this data stream and synchronize it to another free running clock of exactly the same center frequency (8MHz). This clock is absolutely stable but it has no relationship whatsoever with the incoming clock i.e it is not phase locked. Can you suggest a digital based design for doing this to enable it to be implemented in an FPGA so that the output data stream is error free.
I tried using the dual-port RAM concept by using an 8 times the stable system clock to latch the data by generating relevant pulses and then writing this data into the RAM and reading it out on the system clock but there is a burst of errors after a certain time followed by correct data and then a burst and so on. The design works perfectly for a 4 bit repetitive pattern and also for a 16 bit word where the bits can be set to any value. However, for a pseudo-random sequence of 2~23 - 1 the problem persists.
I tried out various options but have not been able to resolve the problem.
The exact design I have used is as follows :
The incoming data is with respect to rising edge of the clock, This rising edge generates an enable to a counter which is running on 8 times the stable system clock. This counter generates two pulses viz one on the 2nd rising edge of the 8 times clock and the other at the 4th rising edge. The first pulse latches the data and increments the write address counter of the dual-port ram. The second pulse then is used as clcok to write this latched data into the Dual-port RAM. This second pulse is also used in conjuction with a flip flop running on the 8 times stable clock but on the negative edge to generate a reset for the counter and enabling circuit. Since the counter has been designed in VHDL the characteristic is that on reset the count and pulses are all set to zero. Thus the flip flop generating the rest also comes out of its active state on the next negative edge. No race around or permanent reset occurs at any point of time. This has been extensively checked out. The enabling circuit works again on the next positive edge and the procedure is repeated. The read from Dual port RAM starts after half the locations are filled up.
The problem that I have been able to trace out is in the writing section. In a Pseudo-random pattern the data latching into RAM is in error occassionally. I subsequently changed the position of pulses to give sufficient time to stabilize but with various combinations tried there is still error.
Can a solution be suggested to accomplish the task of asynchronous to synchronous design ?
Thanks