A new project

[Rhyno56raz]

Im working on a counter which will only count up to ten Im self tough in VHDL so im having lots of trouble shooting problems.
Here is the code if you spot why it wont work plz commit. Thanks



Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity VindingM is
port( Resetn :in std_logic;
OneDollar :in std_logic;
D ut std_logic_vector(3 Downto 0));
end VindingM;
architecture Behavior of VindingM is
signal count: std_logic_vector(3 Downto 0);
signal Q: std_logic_vector(3 Downto 0);
BEGIN


process(OneDollar,Resetn)
BEGIN
IF Resetn = '0' THEN
Count <= "0000";
ELSIF(OneDollar'EVENT AND OneDollar ='1')then
Count <= Count+'1';
end if;
end process;


with count select
D<= "0000" when "0000",
"0001" when "0001",
"0010" when "0010",
"0011" when "0011",
"0100" when "0100",
"0101" when "0101",
"0110" when "0110",
"0111" when "0111",
"1000" when "1000",
"1001" when "1001",
"1010" when others;

end Behavior;

 

[fjodorr]

Please post the compiler error report