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  1. JTRAETS

    Xilinx Pipelined Divider Problem

    I've tested the gated clock now and it solves the problem. What timing is concerned, I'm not sure that can be the problem. The inputs are from accumulators (also cores) these are clocked also. When they give the outputs a counter waits for the division, and takes the quot and sends it to a...
  2. JTRAETS

    Xilinx Pipelined Divider Problem

    Sorry I mean 2 input busses and 1 output bus. I thought that the core was a known product. Here you can find the datasheet: http://www.xilinx.com/ipcenter/catalog/logicore/docs/pipediv_dsp.pdf
  3. JTRAETS

    Xilinx Pipelined Divider Problem

    The core only holds 2 inputs, 1 output and a clock input. The main problem is that it can't be resetted, so it's dividing al the time. I'm sure it's not something general because it seems that I fixed it. I gated the clock input ( I know, not good design practise) so now it's only dividing...
  4. JTRAETS

    Xilinx Pipelined Divider Problem

    Hi, I'm working with the xilinx divider core, it seems to be failing. When I reset the FPGA it sometimes (after about 300 resets) gives back wrong outputs. This will stay this way until it's reloaded. Is anyone else having problems with this core? Greetz Johan

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