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Thanks Mr. VHDLGuy..... I appreciate your kindness to answer my/our questions in this forum. Well, I already turnover my project to the higher engineer. They gave me a new project. Anyway, thanks for your reply.... 'til then!.....

Hallo everyone! Regarding on my project, I'm still doing the design for frame grabber board. As I have an input clock signal which is greater than 50% duty cycle, I need to convert it into 50% duty cycle. I do not know how to implement it in VHDL program. If someone knows how, please teach me...

Sorry for the late reply. Anyway, Thanks for the information. This forum helps me a lot. Thanks again!

Maybe that my mistake, I do not understand yet the difference between synthesizer and simulator. What I mean is I need a clock with a period of 1/7 of the input clock. I think it's not 7x coz if I will make it 7x, time will come that it will not synchronize with the input clock. Thanks again!

I really don't need to know the frequency, it's just my idea on how I can generate a clock that is 1/7 of the input clock. On my case, I don't have to use any external clock signals, only the input clock signal is my reference. Everything should be written in VHDL, that's why I'm studying about...

Thank you for you reply VHDLGuy. I look at the altera's function components and unfortunately the family device I am using does not support PLL components that's why I'm looking a VHDL code for it... Thanks.....

Thanks for the comment. If you know about the LVDS Receiver, I need LVDS Receiver inside of PLD. As a beginner programmer of VHDL, I have an idea, but the problem is implementation. I don't know how can I put in on code. Thanks again!

Here are the clock signals I need to get from a VHDL program. That's the problem, how can I generate those clock signals from inputclk only. _____________________ ______ inputclk => ____| |______________| internal clock signals...

sorry for that, i mean 7 samples only. i'm studying now about pll and LVDS receiver. I hope this will help me but I can't find VHDL file for pll. Thanks!

Thanks! I will try your ideal suggestion. I will search for the PLL of the PLD I'm using. I'm going to use it internally not an output of PLD. I'm just a beginner programmer of VHDL that's why I'm asking for somebody's help. Thanks again!

Thank you for the reply. I need to know the speed of the input clock to the PLD and my problem is I don't know how to count it. I need to divide the clock pulse width into 7 bits. From that, I will get the input data in every bit of it. I don't know how can I implement it in VHDL. Thanks again...

Hallo everyone, I'm doing my project about camera link, and i need to know the code on how to determine the frequency of a clock. the output of the camera goes to the ALTERA PLD. Thanks! c",)-

To everyone, I am programing a VHDL for PLD. Does anyone knows the code or algorithm of generating a new clock with a different duty cycle from a given clock. (For example, the given clock 50MHz has a 50% duty cycle, the output clock should have 50 MHz too but with 85% duty cycle. Thanks!