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Thanks senjed, I think I have heard something like that before. For the time being I have recoded my design to avoid the issue, but I'm sure it will appear again before too long :) Chris.

Thanks for your help VHDLguy. With regard to the hold signal, it is partially true that I don't care about clock events during the hold, but I need to know that they have occurred so that they can be actioned when hold disappears. Maybe a timing diagram would help to explain: clock...

Sorry, that is the wrong error message. The correct one is: "ERROR:Xst:677 - controller.vhd line 330: Illegal constants on arithmetic operators." Apologies for being dumb :) Chris.

Hi, I am trying to add an integer to an integer variable in VHDL, but when I try to synthesise it in XST I get: "ERROR:Xst:1549 - controller.vhd line 331: Range bound must be a constant." I have a bus (7 downto 0) that I convert to an integer using CONV_INTEGER, then try to add it...

BTW, the idea of the overflow signal is that it should go high upon overflow, and stay high until reset. Would this code not achieve this? It seems to simulate OK, and I can't see why the code would not do it...?

Thanks for your prompt reply Berett. Maybe I need to clarify what I'm trying to do... Basically the counter value will be read by some other process, but I want to make sure that the counter value can never change whilst reading it. (There may be better ways to do this, but it's more for...

Thanks Berett, your spell has helped me considerably :) In order to produce cleaner, more understandable code, I decided to take the 'hold' functionality out of the counter and write a wrapper that implements the 'hold' functionality outside of the counter. (Another reason for doing this is...

Hi, I am trying to synthesise the following VHDL description of a 16-bit counter using XST (in Xilinx ISE Webpack), but I am getting a synthesis error - "Bad synchronous description" on signal 'tmpcount'. Could anyone please give me a clue as to where I have gone wrong? Thanks...

Hi, I am currently developing an 8-channel event logger in VHDL to replace an existing 8051 assembly routine that is too slow. When completed, the PLD will interface with the 8051, which will pass commands over a bus and expect the logger to respond with the timer values that it has logged for...