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Simple "if" costs 72MB memory???
By the way, I've tried to modify "bit" to "STD_LOGIC". The Map Report is identical as previous. :) The following is part of Place & Route Report. Device utilization summary: Number of External IOBs 4 out of 172 2% Number of LOCed External IOBs 0 out of 4 0%... -
Simple "if" costs 72MB memory???
Thank you for your reply! I am a new user to Xilinx ISE tool, also a novice at programming in VHDL... There are several reports, such as Synthesis Report, Translation Report, Map Report and Place & Route Report. Which one shall I look at if I want to know the utilization of the FPGA? The... -
Simple "if" costs 72MB memory???
Hi, all, I just started playing around with Xilinx ISE 6.2i. The logic of my testing VHDL code is very simple: 1 if statement and 2 assignment statements. However, the "Place & Route" reports my that the Peak Memory Usage is 72 MB! The "stopwatch" tutorial provided by Xilinx has more... -
How to make process to execute when S'active?
I'd like to execute one process whenever the signal S is active (that is, a new value is assigned to S, but not necessary to be different from the old value of S). How to make that? If just put S in the process sensitive list, the process will only be executed when S has an event (that is, S... -
I am a beginner. Can anyone tell me what's wrong with my simple code?
Oh, probably I know what's wrong... I shall use behavioral modeling here. Therefore, I need to define a process. Am I right? -
I am a beginner. Can anyone tell me what's wrong with my simple code?
Dear all, I am a beginning learner of VHDL. My following simple code got compile error, but I have no idea at all... Can anyone tell me what's wrong with it? The compile error message is also attached. Thanks a lot!!! Peggy entity bt_vertex is port (A: in character; B,C: out character); end...
