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Type mismatch problem
You must typecast them. U can use ready function like to_integer(unsigned( google it and you will find good guides -
ghdl: no definition for "and" and "or" operator
You making the wrong use of "and" and "or" and confuse the use of vectors and bits. For row0 that is a vector u must use "&" like (not D(3) & not D(2) ) and so on. For your output you use vectors where there should be bits. Y(3) <= '0' or row8(somebit) or rowD(somebit) or row3(somebit); Do... -
Ford Tail lights VHDL program
Please post what you wan´t help with. It´s not so simple for me to understand what a Ford tail light program does. I´ll help you on the way if you post what you have written so far. -
=> and <=
Hi! If you assign a value you use: A <= B; --Then A will get the value of B, "<=" will produce a flip-flop. => you use in example: port map(clk => clk) -
