after some idea come to me i change my code to this
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI : in std_logic;
PO : out std_logic_vector(3 downto 0));
end shift;
architecture archi of shift is
signal tmp1: std_logic_vector(7 downto 0);
signal tmp2: std_logic_vector(3...
hello
my project is synchronous communication between two 16v8. THe first 16v8 would take a signal from an 8 dill switch and using serial communication will communicate with the second one 16v8. From the second 16v8 a bcd decoder 74ls47 will be connected and then a 7 segment display.
So when...
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