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New to VHDL
Hi, There are already many inbuilt examples in XILINX webpack. You can used Modelsim Xilinx Starter (Free edition from XILINX) to simulate those projects and get some feelings. if you have any further question just ask mptech -
detect clock signal in VHDL
Hi friends, I need to detect a clock signal and want to generate a flag for following circuit. My requirement is like: 1. when there is a clock signal the flag should set to 0 2. when there is no clock signal then flag should set to 1. I tried to lots of method but have a problem with clock... -
Altera VHDL question
better to separate all bits of logic_vector like below and give to std_logic output: tmp1<= MUX_SEL(0); tmp2<=MUX_SEL(1); and so on; thus you will get all bits of logic_vector as separated std_logic.
