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- Users: HosseinMoradi
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VHDL Models
Dear a3debut the only diffrence that they have is in synthesis. for example some of instructions that are used for simulating can't be synthesised.EXP: blok and guarded in vhdl. or power(**) function!!! you don't have any hardware that do this but you can use multiplier -first you should design...- HosseinMoradi
- Post #2
- Forum: VHDL
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vhdl roms
Dear Kasvela, in a process statement if you are using vhdl language you can defien a varity of constants in declaration part of process and then in it's body which is sensitive to OE pin or rd pin-that you've defined in the entity part-you use some addresses with if()statement or a case and then...- HosseinMoradi
- Post #3
- Forum: VHDL
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For loop synthesis errors
Dear guy, If you only want ot simulate this code you won't have any problem but for synthesising you should know that you can't use a variable for right bound of range in a for loop you can only use canstants as bound in a for loop. soyou can use acse statement and use all the values that your...- HosseinMoradi
- Post #3
- Forum: VHDL
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For loop synthesis errors
Dear guy, If you only want ot simulate this code you won't have any problem but for synthesising you should know that you can't use a variable for right bound of range in a for loop you can only use canstants as bound in a for loop. Regards, Hossein Moradi- HosseinMoradi
- Post #2
- Forum: VHDL
