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- Users: Srika
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Logic space
If at all u could be a bit more clear,I'd appreciate that? sri -
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Identifying carraige return and newline in code
the solution given by jtm111 is ideal no doubt about that -
need help with synchronous input vs. clock
The first solution u've supplied is not a proper solution because if u delay the clock pulse then the parallelism is lost.I'd suggest to make the second process sensitive to the first output signal,and check for the clock'event and clk=1 in the same.This is the general solution of the problem u... -
rising and falling edge trigger
No the code is not synthesisable.But in a simulation point of view,This is correct -
rising and falling edge trigger
Of course u can do it Clk'event and (clk='1' or clk='0') This probably shouldn't have any problem.Any way I don't get the purpose of u trying this.If u could tell me the exact context I'd appreciate it. srikanth -
clock multiplication
Hi Tell me the mode u r creating the clock .r u using the standard IEEE clock or u r writing a test bench for clock generation.Anyway a multplication of clock does not make sense as there is a change in the very code(here the delay u r giving to set the frequency).All u can do is while u r... -
question on file input output in vhdl
Hi I'm trying to implement data encryption in VHDL. As I'm at the verge of completion.I have to implement the following. It would be very helpful to give me an answer to the following question I want to read a text file.Convert it into Bit vector.Collect a frame of 64 bits and send it for...
