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Thank you very much dsimon19 for your suggestions and interest. I'll consider your opinions and try to work carefully. Take Care, Oppenheimer

Hi dsimon19, Thank you verymuch, because of your suggestions and ideas. I have realised what you wanted to imply by 'warining message'. Yes there are lots of warning without any error.(Ahhahh!)But, what can be the reason I "could not" find the reason! It drives me crazy(Puuaahh!!)I have tried...

Hi All, I wanna ask something about creating different clock frequencies. Basicly I have 48 Mhz clock signal on my CPLD board. But I need lower frequencies (about 100Hz) to scan more than one seven segment display. I have used different code styles but could not get the signals. "Loop", "after"...

Thanks for your valuable suggestions, I have revized the code and collected all signals under the name of Cclk. signal Cclk: std_logic ; Command line is: Cclk<= UpBtn or DownBtn or Rst or clk ; process (Cclk,bcd) .. ...

Thanks blacktom, I have revised the code and thought about your suggestion. But now I have another problem which is about signal "bcd". On the other hand, when I tried to get out case statemnet from the process( to put it another process which has a sensitivity list as "bcd") it gives another...

Hi All, I'm one of the new members of this discussion platform. And I'm also beginner about the VHDL. I have XLINX CoolRunner-II CPLD bord and I'm trying to learn VHDL. Nowadays, I design a simple counter code to count from 0 to 9 on the seven segment display. But there is an error which I...