Tek-Tips is the largest IT community on the Internet today!
Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!
-
Congratulations Mike Lewis on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!
-
Am I implementing a LSFR correct?
The first thing I ever designed in vhdl was a PRBS tester which had an LFSR at its core. Your state machine process looks good to me but in your LFSR process I am not sure why you are using: linear_feedback <= (not LSFR(1) xor LSFR(0)); I'm not too sure what initial value you use as a seed... -
LAST_VALUE attribute
hi there, am trying to synthesis a generic clock divider I have created. it works fine in simulation with modelsim but xilinx syntheses tool xst is not happy. - see code below: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity generic_clk_divider is generic (... -
Using a process inside a procedure
oops, missed out variable declaration in above code. looks like my brackets are a bit dodgy too. don't forget: variable Qout : integer range 0 to 11; before begin block. gstar -
Using a process inside a procedure
Hi there, I'm a bit of a newbie to vhdl but I have my doulos golden guide beside me and the answer your looking for is no, you can't put a process inside a procedure. Processes can only be used in: architecture - between begin/end generate - between begin/end entity - between begin/end...
